Z8018233FSC datasheet(63/109 Pages) ZILOG

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Z80182/Z8L182

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DS971820600

16550 MIMIC INTERFACE REGISTERS

MIMIC Master Control Register (MMC)

The 16550 MIMIC interface is controlled by the MMC

such as using the 8-bit counters, DMA accesses, and

which IRQ structure is used with the PC/XT/AT.

000000

VIS Vector Include Status

0 Mode 0 Interrupts

1 Mode 2 Interrupts

HINTR

00 Normal

01 Wire And

10 Out 2 Control

11 Reserved

Rx DMA

0=Chan 0 Z180

1=Chan 1 Z180

Tx DMA

0=Chan 1 Z180

1=Chan 0 Z180

Rx DMA Enable

Tx DMA Enable

Rx Timer Enable

Tx Timer Enable

Figure 60. MIMIC Master Control Register

(Z180 MPU Read/Write, Address xxFFH)

Bit 7 Transmit Emulation Delay Counter Enable

(Read/Write)

If bit 7 is set to 1, it enables the transmit delay timer. When

the Z180 reads the Transmit Register, it loads the transmit

delay timer from the Transmit Time Constant Register and

enables the timer to count down to zero. This timer delays

setting the Transmit Holding Register Empty (THRE) bit

until the timer times out. If this bit is 0, then THRE is set

immediately on a Z180 read of the Transmit Register. This

bit also enables the emulation timer used in Transmitter

Double Buffering.

Bit 6 Receive Emulation Delay Counter Enable

(Read/Write)

If bit 6 is set to 1, it enables the receive delay timer. When

the Z180 writes to the Receive Buffer, it loads the receive

delay timer from the Receive Time Constant Register and

enables the timer to count down to zero. This timer delays

setting the Data Ready (DR) bit in the LSR until the timer

times out. If this bit is 0 then DR is set immediately on a Z180

write to the Receive Buffer.

Both counters are single pass and stop on a count of Zero.

Their purpose is to delay data transfer just as if the 16550

UART had to shift the data in and out. This is provided to

alleviate any software problems a high speed continuous

data transfer might cause to existing software. If this is not

a concern, then data can be read and written as fast as the

two machines can access the devices. In FIFO mode of

operation , the timers are used to delay the status to the PC

interface by the time required to actually shift the characters

out, or in, if an actual UART were present.

Bit 5 Transmit DMA Enable (Read/Write)

If this bit is set to 1, it enables the Transmit DMA function.

Bit 4 Receive DMA Enable (Read/Write)

If this bit is set to 1, it enables the Receive DMA function.

Bit 3 Receive DMA Channel Select (Read/Write)

If bit 3 is set to 0, then Receive DMA transfer is done

through Z180 DMA channel 0 and the Transmit DMA is

done through DMA channel 1. If bit 3 is set to 1, then

Receive DMA transfer is done through Z180 DMA channel

1 and the Transmit DMA is done through DMA channel 0.

Bits 2,1 Interrupt Select (Read/Write).

See Table 15.

Bit 0 Vector Include Status (Read/Write)

This bit is used to select the interrupt response mode of the

Z180. A 0 in this bit enables Mode 0 interrupts; a 1 enables

Mode 2 response.

Table 15. MIMIC Master Control Register

Interrupt Select

Bit 2

Bit 1

HINTR Function

HINTR is set to normal 16550 MIMIC mode.

A fully driven output is required when

external priority arbiters are used.

A wired AND condition on the HINTR pin is

possible to the PC/XT/AT. The interrupt

is active High with only the pull-up

of the HINTR pin driving; otherwise this

pin is tri-state. Wired AND is needed when

an external arbiter is not available.

HINTR is driven when out 2 of the Modem

Control Register is 1. HINTR is tri-state

when MCR out 2 is 0.

RESERVED

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