Z8018233FSC datasheet(53/109 Pages) ZILOG

53 / 109 page

3-53

Z80182/Z8L182

ZILOG INTELLIGENT PERIPHERAL

PRELIMINARY

Zilog

DS971820600

D6 D5

Auto Tx Flag

WR 7' Prime

Auto EOM Reset

Auto RTS Deactivation

Rx FIFO Int Level

DTR/REQ Timing Mode

Tx FIFO Int Level

Extended Read Enable

32-bit CRC Enable

Write Register 10

6-Bit//8-Bit Sync

NRZ

NRZI

FM1 (Transition = 1)

FM0 (Transition = 0)

Loop Mode

Abort//Flag On Underrun

Mark//Flag Idle

Go Active On Poll

CRC Preset I//O

Write Register 11

/TRxC Out = Xtal Output

/TRxC Out = Transmit Clock

/TRxC Out = BR Generator Output

/TRxC Out = DPLL Output

/TRxC O/I

Transmit Clock = /RTxC Pin

Transmit Clock = /TRxC Pin

Transmit Clock = BR Generator Output

Transmit Clock = DPLL Output

Receive Clock = /RTxC Pin

Receive Clock = /TRxC Pin

Receive Clock = BR Generator Output

Receive Clock = DPLL Output

/RTxC Xtal//No Xtal

D3 D2

Write Register 9

VIS

No Reset

Not used

Channel Reset

Force Hardware Reset

DLC

MIE

Status High//Status Low

Software INTACK Enable

Figure 52. Write Register Bit Functions (Continued)

Z8018233FSC 数据表(PDF) 53 Page - Zilog, Inc.

Z8018233FSC 数据表(HTML) 53 Page - Zilog, Inc.

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