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Z8018233FSC 数据表(PDF) 41 Page - Zilog, Inc.

部件名 Z8018233FSC
功能描述  ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP??
PDF  109 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  ZILOG [Zilog, Inc.]
网页  http://www.zilog.com
标志 ZILOG - Zilog, Inc.

Z8018233FSC 数据表(HTML) 41 Page - Zilog, Inc.

Back Button Z8018233FSC Datasheet HTML 37Page - Zilog, Inc. Z8018233FSC Datasheet HTML 38Page - Zilog, Inc. Z8018233FSC Datasheet HTML 39Page - Zilog, Inc. Z8018233FSC Datasheet HTML 40Page - Zilog, Inc. Z8018233FSC Datasheet HTML 41Page - Zilog, Inc. Z8018233FSC Datasheet HTML 42Page - Zilog, Inc. Z8018233FSC Datasheet HTML 43Page - Zilog, Inc. Z8018233FSC Datasheet HTML 44Page - Zilog, Inc. Z8018233FSC Datasheet HTML 45Page - Zilog, Inc. Next Button
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3-41
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
PRELIMINARY
Zilog
DS971820600
MWI1
MWI0
DMS0
DIM1
DIM0
111
R/W
1
R/W
00
R/W
00
R/W
DMA Ch 1 I/O Memory
Mode Select
Addr 32H
Bit
Upon Reset
DMS1
IWI0
/DREQi Select, i = 1, 0
I/0 Wait Insertion
IWI1
DCNTL
R/W
R/W
R/W
R/W
R/W
Memory Wait Insertion
DM1, 0
00
01
10
11
Transfer Mode
M - I/O
M - I/O
I/O - M
I/O - M
Address Increment/Decrement
DMSi
1
0
Sense
Edge Sense
Level Sense
MWI1, 0
00
01
10
11
No. of Wait States
0
1
2
3
IWI1, 0
00
01
10
11
No. of Wait States
1
2
3
4
MAR1+1
MAR1-1
IAR1 Fixed
IAR1 Fixed
IAR1 Fixed
IAR1 Fixed
MAR1+1
MAR1-1
*
Note:
* If using ROM/RAM Chip Select wait state generators,
the Z180 wait state generator should be set to 0.
Figure 42. DMA/WAIT Control Register



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