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Z8018233FSC 数据表(PDF) 100 Page - Zilog, Inc. |
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Z8018233FSC 数据表(HTML) 100 Page - Zilog, Inc. |
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100 / 109 page ![]() 3-100 Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL PRELIMINARY Zilog DS971820600 ESCC External Bus Master Timing 1 2 Valid ESCC Addr * IORQ /RD or /WR DTR/REQ Request Figure 109. ESCC External Bus Master Timing Table G. External Bus Master Interface Timing (SCC Related Timing) Z8L182 Z80182 20 MHz 33 MHz No. Symbol Parameter Min Max Min Max Units Notes 1 TrC Valid Access Recovery Time 4TcC 4TcC ns [1] 2 TdRDr(REQ) /RD Rise to /DTR//REQ Not Valid Delay 4TcC 4TcC ns Notes: These AC parameter values are preliminary and are subject to change without notice. [1] Applies only between transactions involving the ESCC. T CC = ESCC clock period time |
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