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Z8018233FSC 数据表(PDF) 103 Page - Zilog, Inc. |
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Z8018233FSC 数据表(HTML) 103 Page - Zilog, Inc. |
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103 / 109 page ![]() 3-103 Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL PRELIMINARY Zilog DS971820600 /HRD /HDDIS 13 Figure 113. Driver Enable Timing Table J. Driver Enable Timing Z8L182 Z80182 20 MHz 33 MHz No. Sym Parameter Min Max Min Max Units 13 tRDD /HRD to Driver Enable/Disable 60 60 ns Note: These AC parameter values are preliminary and are subject to change without notice. Figure 114. Interrupt Timing RCVR FIFO 14 14 15 15 /WR (MPU) RBR HINTR (Trigger Level) HINTR (Line Status RDR /HRD LSR /HRD RBR |
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