Z8018233FSC datasheet(59/109 Pages) ZILOG

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Z80182/Z8L182

ZILOG INTELLIGENT PERIPHERAL

PRELIMINARY

Zilog

DS971820600

Z182 MISCELLANEOUS CONTROL AND INTERFACE REGISTERS

Bit 3 Disable ROMs

If this bit is 1, it disables the ROMCS pin. If it is 0, addresses

below the ROM boundary set by the ROMBR register will

cause the ROMCS pin to go Low.

Bit 2 Tri-Muxed Pins Select

The Z80182/Z8L182 has three pins that are triple

multiplexed and controlled by bit 2 and bit 1. Table 14

shows the different modes.

Table 14. SCR Control for Triple Multiplexed Pins

Bit 2

Bit 1

System Configuration Register

/TEND1,TxS,CKS

/RTSB,(/DTR//REQB),(/W//REQB)

/HRxRDY,//HTxRDY,HINTR

Bit 1 ESCC™ Channel B/MIMIC

If this bit is 0, Mode 0 is selected.

If this bit is 1, Mode 1 is selected.

Mode 0:

Channel A ESCC Enabled

Channel B ESCC Enabled

PIA Port Enabled

16550 MIMIC Interface Disabled

Mode 1:

Channel A ESCC enabled

Channel B outputs disabled

PIA disabled

16550 MIMIC Interface Enabled

Bit 0 Daisy Chain

This bit is used to set interrupt priority of the ESCC and

16550 MIMIC interface. If it is 0, the ESCC is higher up in

the daisy chain than the 16550 MIMIC interface. If it is 1, the

16550 interface is higher up than the ESCC. Note that

/INT0 is used for both MIMIC and ESCC Interrupts.

/RAMCS AND /ROMCS REGISTERS

To assist decoding of ROM and RAM blocks of memory,

three more registers and two pins have been added to the

Z80182/Z8L182. The two pins are /ROMCS and /RAMCS.

The three registers are RAMUBR, RAMLBR and ROMBR.

11111

Upon reset

A19-A12

Figure 55. RAMUBR

(Z180 MPU Read/Write, Address xxE6H)

11111

Upon reset

A19-A12

Figure 56. RAMLBR

(Z180 MPU Read/Write, Address xxE7H)

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