Z8018233FSC datasheet(20/109 Pages) ZILOG

20 / 109 page

3-20

Z80182/Z8L182

ZILOG INTELLIGENT PERIPHERAL

PRELIMINARY

Zilog

DS971820600

Transmit Logic

Channel A

Receive and Transmit Clock Multipexer

Transmit FIFO

4 Bytes

Transmit MUX

Data Encoding & CRC

Generation

Digital

Phase-Locked

Loop

Baud Rate

Generator

Crystal

Oscillator

Amplifier

Modem/Control Logic

Receive MUX

CRC Checker,

Data Decode &

Sync Character

Detection

Rec. Status*

FIFO

Rec. Data*

FIFO

SDLC Frame Status FIFO

10 x 19

Receive Logic

TxDA

/TRxCA

/RTxCA

/CTSA

/DCDA

/SYNCA

/RTSA

/DTRA//REQA

RxDA

Exploded View

Internal

Control

Logic

Channel A

Channel B

Interrupt

Control

Logic

CPU & DMA

Bus Interface

Databus

Control

Channel A

Channel B

/INT

/INTACK

IEI

IEO

Interrupt

Control

* 8 bytes each

Figure 5. ESCC Block Diagram

Z85230 ESCC™ BLOCK DIAGRAM

For a detailed description of the Z85230 ESCC, refer to the ESCC Technical Manual. The following figure is the block

diagram of the discrete ESCC, which was integrated into the Z182. The /INT line is internally connected to "INTO of the

Z182.

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