USB3320 datasheet(21/70 Pages) MICROCHIP

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 2014-2015 Microchip Technology Inc.

DS00001792B-page 21

USB3320

In this mode, the REFCLK pin may be driven at the reference clock frequency. Alternatively, the internal oscillator may

be used with an external crystal or resonator as shown in Figure 5-4.

An example of ULPI Output Clock Mode is shown in Figure 8-1.

After the PLL has locked to the correct frequency, the USB3320 generates the 60MHz ULPI clock on the CLKOUT pin,

and de-asserts DIR to indicate that the PLL is locked. The USB3320 is ensured to start the clock within the time specified

in Table 4-2, and it will be accurate to within ±500ppm. For Host applications the ULPI AutoResume bit should be

enabled. This is described in Section 6.2.4.4.

When using ULPI Output Clock Mode, the edges of the reference clock do not need to be aligned in any way to the ULPI

interface signals; in other words, there is no need to align the phase of the REFCLK and the CLKOUT.

5.4.2

REFCLK AMPLITUDE

The reference clock is connected to the REFCLK pin as shown in the application diagrams, Figure 8-1, Figure 8-2 and

Figure 8-3. The REFCLK pin is designed to be driven with a square wave from 0V to VDD18, but can be driven with a

square wave from 0V to as high as 3.6V. The USB3320 uses only the positive edge of the REFCLK.

If a digital reference is not available, the REFCLK pin can be driven by an analog sine wave that is AC coupled into the

REFCLK

pin. If using an analog clock, the DC bias should be set at the mid-point of the VDD18 supply using a bias

circuit as shown in Figure 5-5. The amplitude must be greater than 300mV peak to peak. The component values pro-

vided in Figure 5-5 are for example only. The actual values should be selected to satisfy system requirements.

The REFCLK amplitude must comply with the signal amplitudes shown in Table 4-4 and the duty cycle in Table 4-2.

FIGURE 5-4:

ULPI OUTPUT CLOCK MODE

FIGURE 5-5:

EXAMPLE OF CIRCUIT USED TO SHIFT A REFERENCE CLOCK COMMON-

MODE VOLTAGE LEVEL

CLKOUT

REFCLK

PHY

From PLL

Link

ULPI Clk In

Resonator

Crystal

and Caps

- or -

CLOAD

Internal

Oscillator

To PLL

Clock

0.1uF

VDD18

To REFCLK pin

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