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USB3320 数据表(PDF) 61 Page - Microchip Technology |
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USB3320 数据表(HTML) 61 Page - Microchip Technology |
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61 / 70 page  2014-2015 Microchip Technology Inc. DS00001792B-page 61 USB3320 FIGURE 8-3: USB3320 APPLICATION DIAGRAM (HOST OR OTG, ULPI OUTPUT CLOCK MODE, 24MHZ) VBUS Switch OUT EN IN 5V VBUS 22 VBAT 21 VDD33 20 ID 23 DM DP 19 18 SPK_L SPK_R 16 15 GND Optional Switched Signal to DP/DM USB Receptacle DM DP ID SHIELD GND VBUS COUT 3.1-5.5V Supply CBYP RVBUS The capacitor CVBUS must be installed on this side of RVBUS. CVBUS RVBUSmust be installed to enable overvoltage protection of the VBUS pin. REFSEL2 14 REFSEL1 11 REFSEL0 8 VDDIO Supply CPEN 17 Link Controller DIR NXT STP CLKIN DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA0 DATA1 RESETB RBIAS DIR NXT STP CLKOUT DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA0 DATA1 13 10 9 7 6 5 4 3 29 2 31 1 RESETB 27 24 RBIAS VDD18 28, 30 1.8V Supply CBYP VDDIO CBYP VDDIO Supply 32 26 25 1M Ω CLOAD Resonator Crystal and Caps - or - REFCLK XO For Host applications (non-OTG), the ID pin should be connected to GND. |
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