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USB3320 数据表(PDF) 53 Page - Microchip Technology |
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USB3320 数据表(HTML) 53 Page - Microchip Technology |
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53 / 70 page ![]() 2014-2015 Microchip Technology Inc. DS00001792B-page 53 USB3320 7.1.1.10 USB Interrupt Status Address = 13h (read only) This register dynamically updates to reflect current status of interrupt sources. 7.1.1.11 USB Interrupt Latch Address = 14h (read only with auto clear) Note 7-2 rd: Read Only with auto clear. 7.1.1.12 Debug Address = 15h (read only) SessEnd Fall 3 rd/w/s/c 1b Generate an interrupt event notification when SessEnd changes from high to low. IdGnd Fall 4 rd/w/s/c 1b Generate an interrupt event notification when IdGnd changes from high to low. Reserved 7:5 rd 000b Read only, 0. Field Name Bit Access Default Description HostDisconnect 0 rd 0b Current value of the UTMI+ Hi-Speed Hostdisconnect output. Applicable only in host mode. VbusValid 1 rd 0b Current value of the UTMI+ Vbusvalid output. SessValid 2 rd 0b Current value of the UTMI+ SessValid output. SessEnd 3 rd 0b Current value of the UTMI+ SessEnd output. IdGnd 4 rd 0b Current value of the UTMI+ IdGnd output. Reserved 7:5 rd 000b Read only, 0. Note: The default conditions will match the current status of the comparators. The values shown are for an unat- tached OTG device. Field Name Bit Access Default Description HostDisconnect Latch 0 rd (Note 7-2) 0b Set to 1b by the transceiver when an unmasked event occurs on Hostdisconnect. Cleared when this register is read. Applicable only in host mode. VbusValid Latch 1 rd (Note 7-2) 0b Set to 1b by the transceiver when an unmasked event occurs on VbusValid. Cleared when this register is read. SessValid Latch 2 rd (Note 7-2) 0b Set to 1b by the transceiver when an unmasked event occurs on SessValid. Cleared when this register is read. SessEnd Latch 3rd (Note 7-2) 0b Set to 1b by the transceiver when an unmasked event occurs on SessEnd. Cleared when this register is read. IdGnd Latch 4rd (Note 7-2) 0b Set to 1b by the transceiver when an unmasked event occurs on IdGnd. Cleared when this register is read. Reserved 7:5 rd 000b Read only, 0. Field Name Bit Access Default Description Linestate0 0 rd 0b Contains the current value of Linestate[0]. Linestate1 1 rd 0b Contains the current value of Linestate[1]. Reserved 7:2 rd 000000b Read only, 0. Field Name Bit Access Default Description |
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