USB3320 datasheet(6/70 Pages) MICROCHIP

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USB3320

DS00001792B-page 6

 2014-2015 Microchip Technology Inc.

2.0

USB3320 PIN LOCATIONS AND DEFINITIONS

2.1

USB3320 Pin Locations and Descriptions

2.1.1

PACKAGE DIAGRAM WITH PIN LOCATIONS

The illustration below is viewed from the top of the package.

2.1.2

PIN DEFINITIONS

The following table details the pin definitions for the figure above.

FIGURE 2-1:

USB3320 PIN LOCATIONS - TOP VIEW

TABLE 2-1:

USB3320 PIN DESCRIPTION

Name

Direction/

Type

Active

Level

Description

1CLKOUT

Output,

CMOS

N/A

ULPI Output Clock Mode:

60MHz ULPI clock output. All ULPI signals

are driven synchronous to the rising edge

of this clock.

ULPI Input Clock Mode:

This pin is connected to VDDIO to

configure 60MHz ULPI Input Clock mode

as described in Section 5.4.1.

Following POR or hardware reset, the

voltage at CLKOUT must not exceed

VIH_ED as provided inTable 4-4.

2NXT

Output,

CMOS

High

The transceiver asserts NXT to throttle the

data. When the Link is sending data to the

transceiver, NXT indicates when the

current byte has been accepted by the

transceiver. The Link places the next byte

on the data bus in the following clock

cycle.

DATA[0]

I/O,

CMOS

N/A

ULPI bi-directional data bus.

CLKOUT

NXT

DATA0

DATA1

DATA2

DATA3

REFSEL0

DATA4

RBIAS

CPEN

VBUS

VBAT

VDD33

USB3300

Hi-Speed USB2

ULPI PHY

32 Pin QFN

Hi-Speed USB

ULPI PHY

32 Pin QFN

GND FLAG

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