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USB3320 数据表(PDF) 36 Page - Microchip Technology |
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USB3320 数据表(HTML) 36 Page - Microchip Technology |
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36 / 70 page ![]() USB3320 DS00001792B-page 36 2014-2015 Microchip Technology Inc. 6.2.1 ULPI REGISTER WRITE A ULPI register write operation is given in Figure 6-3. The TXD command with a register write DATA[7:6] = 10b is driven by the Link at T0. The register address is encoded into DATA[5:0] of the TXD CMD byte. To write a register, the Link will wait until DIR is low, and at T0, drive the TXD CMD on the data bus. At T2 the transceiver will drive NXT high. On the next rising clock edge, T3, the Link will write the register data. At T4, the transceiver will accept the register data and drive NXT low. The Link will drive an Idle on the bus and drive STP high to signal the end of the data packet. Finally, at T5, the transceiver will latch the data into the register and the Link will pull STP low. NXT is used to control when the Link drives the register data on the bus. DIR is low throughout this transaction since the transceiver is receiving data from the Link. STP is used to end the transaction and data is registered after the de- assertion of STP. After the write operation completes, the Link must drive a ULPI Idle (00h) on the data bus or the USB3320 may decode the bus value as a ULPI command. A ULPI extended register write operation is shown in Figure 6-4. To write an extended register, the Link will wait until DIR is low, and at T0, drive the TXD CMD on the data bus. At T2 the transceiver will drive NXT high. On the next clock T3 the Link will drive the extended address. On the next rising clock edge, T4, the Link will write the register data. At T5, the transceiver will accept the register data and drive NXT low. The Link will drive an Idle on the bus and drive STP high to signal the end of the data packet. Finally, at T5, the transceiver will latch the data into the register. The Link will pull STP low. FIGURE 6-3: ULPI REGISTER WRITE IN SYNCHRONOUS MODE DIR CLK DATA[7:0] STP NXT TXD CMD (reg write) Idle Reg Data[n] Idle ULPI Register Reg Data [n-1] Reg Data [n] T0 T1 T2 T3 T5 T4 T6 |
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