USB3320 datasheet(19/70 Pages) MICROCHIP

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DS00001792B-page 19

USB3320

Note 1:

This is the same as Table 40, Section 4.4 of the ULPI 1.1 specification.

USB3320 does not support operation as an upstream hub port. See Section 6.2.4.3, "UTMI+ Level 3".

Note 5-1

The transceiver operation is not ensured in a combination that is not defined.

The USB3320 uses the 27% resistor ECN resistor tolerances. The resistor values are shown in Table 4-5.

5.3

Bias Generator

This block consists of an internal bandgap reference circuit used for generating the driver current and the biasing of the

analog circuits. This block requires an external 8.06K

Ω, 1% tolerance, reference resistor connected from RBIAS to

ground. This resistor should be placed as close as possible to the USB3320 to minimize the trace length. The nominal

voltage at RBIAS is 0.8V +/- 10% and therefore the resistor will dissipate approximately 80

μW of power.

5.4

Integrated Low Jitter PLL

The USB3320 uses an integrated low jitter phase locked loop (PLL) to provide a clean 480MHz clock required for HS

USB signal quality. This clock is used by the transceiver during both transmit and receive. The USB3320 PLL requires

an accurate frequency reference to be driven on the REFCLK pin.

5.4.1

REFCLK MODE SELECTION

The USB3320 is designed to operate in one of two available modes as shown in Table 5-2. In the first mode, a 60MHz

ULPI clock is driven on the REFCLK pin as described in Section 5.4.1.1. In the second mode, the USB3320 generates

the ULPI clock as described in Section 5.4.1.2. When using the second mode, the frequency of the reference clock is

configured by REFSEL[2], REFSEL[1] and REFSEL[0] as described in Section 5.10.

During start-up, the USB3320 monitors the CLKOUT pin to determine which mode has been configured as described

in Section 5.4.1.1.

Peripheral Test J/Test K

00b

10b

OTG device, Peripheral Chirp

00b

10b

OTG device, Peripheral HS

00b

OTG device, Peripheral FS

01b

00b

OTG device, Peripheral HS/FS Suspend

01b

00b

OTG device, Peripheral HS/FS Resume

01b

10b

OTG device, Peripheral Test J/Test K

00b

10b

Any combination not defined above Note 5-

TABLE 5-2:

REFCLK MODES

Mode

REFCLK

Frequency

ULPI Clock Description

ULPI Input Clock Mode

60Mhz

Sourced by Link, driven on the REFCLK pin

ULPI Output Clock

Mode

Table 5-10

Sourced by USB3320 at the CLKOUT pin

TABLE 5-1:

DP/DM TERMINATION VS. SIGNALING MODE (CONTINUED)

Signaling Mode

ULPI Register Settings

USB3320 Termination Resistor

Settings

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