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USB3320 数据表(PDF) 7 Page - Microchip Technology |
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USB3320 数据表(HTML) 7 Page - Microchip Technology |
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7 / 70 page ![]() 2014-2015 Microchip Technology Inc. DS00001792B-page 7 USB3320 4 DATA[1] I/O, CMOS N/A ULPI bi-directional data bus. 5 DATA[2] I/O, CMOS N/A ULPI bi-directional data bus. 6 DATA[3] I/O, CMOS N/A ULPI bi-directional data bus. 7 DATA[4] I/O, CMOS N/A ULPI bi-directional data bus. 8 REFSEL[0] Input, CMOS N/A This signal, along with REFSEL[1] and REFSEL[2] selects one of the available reference frequencies as defined in Table 5-10. Note: This signal must be tied to VDDIO when in ULPI 60MHz REFCLK IN mode. 9 DATA[5] I/O, CMOS N/A ULPI bi-directional data bus. 10 DATA[6] I/O, CMOS N/A ULPI bi-directional data bus. 11 REFSEL[1] Input, CMOS N/A This signal, along with REFSEL[0] and REFSEL[2] selects one of the available reference frequencies as defined in Table 5-10. Note: This signal must be tied to VDDIO when in ULPI 60MHz REFCLK IN mode. 12 N/C N/A This pin must not be connected. 13 DATA[7] I/O, CMOS N/A ULPI bi-directional data bus. 14 REFSEL[2] Input, CMOS N/A This signal, along with REFSEL[0] and REFSEL[1] selects one of the available reference frequencies as defined in Table 5-10. Note: This signal must be tied to VDDIO when in ULPI 60MHz REFCLK IN mode. 15 SPK_L I/O, Analog N/A USB switch in/out for DM signals 16 SPK_R I/O, Analog N/A USB switch in/out for DP signals 17 CPEN Output, CMOS N/A External 5V supply enable. Controls the external VBUS power switch. CPEN is low on POR. 18 DP I/O, Analog N/A D+ pin of the USB cable. 19 DM I/O, Analog N/A D- pin of the USB cable. 20 VDD33 Power N/A 3.3V Regulator Output. A 2.2uF (<1 ohm ESR) bypass capacitor to ground is required for regulator stability. The bypass capacitor should be placed as close as possible to the USB3320. 21 VBAT Power N/A Regulator input. TABLE 2-1: USB3320 PIN DESCRIPTION (CONTINUED) Pin Name Direction/ Type Active Level Description |
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