USB3320 datasheet(33/70 Pages) MICROCHIP

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DS00001792B-page 33

USB3320

6.0

ULPI OPERATION

6.1

Overview

The USB3320 uses the industry standard ULPI digital interface to facilitate communication between the USB Trans-

ceiver (PHY) and Link (device controller). The ULPI interface is designed to reduce the number of pins required to con-

nect a discrete USB Transceiver to an ASIC or digital controller. For example, a full UTMI+ Level 3 OTG interface

requires 54 signals while a ULPI interface requires only 12 signals.

The ULPI interface is documented completely in the “UTMI+ Low Pin Interface (ULPI) Specification Revision 1.1”. The

following sections describe the operating modes of the USB3320 digital interface.

Figure 6-1 illustrates the block diagram of the ULPI digital functions. It should be noted that this USB3320 does not use

a “ULPI wrapper” around a UTMI+ PHY core as the ULPI specification implies.

The advantage of a “wrapper less” architecture is that the USB3320 has a lower USB latency than a design which must

first register signals into the PHY’s wrapper before the transfer to the PHY core. A low latency PHY allows a Link to use

a wrapper around a UTMI Link and still make the required USB turn-around timing given in the USB 2.0 specification.

FIGURE 6-1:

ULPI DIGITAL BLOCK DIAGRAM

NOTE:

The ULPI interface

is a wrapperless

design.

POR

ULPI Register Array

Interrupt Control

Data[7:0]

High Speed TX

Full Speed TX

Low Speed TX

High Speed Data

Recovery

Full / Low Speed

Data Recovery

ULPI Protocol

Block

HS Tx Data

FS/LS Tx Data

HS RX Data

FS/LS Data

DIR

NXT

STP

Tx Data

Rx Data

USB Transmit and Receive Logic

RESETB

Rid State

Machine

To RX

Analog

To TX

Analog

OTG

Analog

To USB

Audio

Analog

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