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USB3320 数据表(PDF) 18 Page - Microchip Technology |
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USB3320 数据表(HTML) 18 Page - Microchip Technology |
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18 / 70 page  USB3320 DS00001792B-page 18 2014-2015 Microchip Technology Inc. 5.2.2 TERMINATION RESISTORS The USB3320 transceiver fully integrates all of the USB termination resistors on both DP and DM. This includes 1.5kΩ pull-up resistors, 15kΩ pull-down resistors and the 45Ω high speed termination resistors. These resistors require no tun- ing or trimming by the Link. The state of the resistors is determined by the operating mode of the transceiver when oper- ating in synchronous mode. The XcvrSelect[1:0], TermSelect and OpMode[1:0] bits in the Function Control register, and the DpPulldown and DmPulldown bits in the OTG Control register control the configuration. The possible valid resistor combinations are shown in Table 5-1, and operation is maintained in only the configurations shown. If a ULPI Register Setting is config- ured that does not match a setting in the table, the transceiver operation is not ensured and the settings in the last row of Table 5-1 will be used. • RPU_DP_EN activates the 1.5kΩ DP pull-up resistor • RPU_DM_EN activates the 1.5kΩ DM pull-up resistor • RPD_DP_EN activates the 15kΩ DP pull-down resistor • RPD_DM_EN activates the 15kΩ DM pull-down resistor • HSTERM_EN activates the 45Ω DP and DM high speed termination resistors The USB3320 also includes two DP and DM pull-up resistors described in Section 5.8. TABLE 5-1: DP/DM TERMINATION VS. SIGNALING MODE Signaling Mode ULPI Register Settings USB3320 Termination Resistor Settings General Settings Tri-State Drivers XXb Xb 01b Xb Xb 0b0b0b0b0b Power-up or VBUS < VSESSEND 01b 0b 00b1b 1b 0b0b1b1b0b Host Settings Host Chirp 00b 0b 10b1b 1b 0b0b1b1b1b Host Hi-Speed 00b 0b 00b1b 1b 0b0b1b1b1b Host Full Speed X1b 1b 00b1b 1b 0b0b1b1b0b Host HS/FS Suspend 01b 1b 00b1b 1b 0b0b1b1b0b Host HS/FS Resume 01b 1b 10b1b 1b 0b0b1b1b0b Host low Speed 10b 1b 00b1b 1b 0b0b1b1b0b Host LS Suspend 10b 1b 00b 1b 1b 0b 0b 1b 1b 0b Host LS Resume 10b 1b 10b1b 1b 0b0b1b1b0b Host Test J/Test_K 00b 0b 10b1b 1b 0b0b1b1b1b Peripheral Settings Peripheral Chirp 00b 1b 10b 0b 0b 1b 0b 0b 0b 0b Peripheral HS 00b 0b 00b 0b 0b 0b 0b 0b 0b 1b Peripheral FS 01b 1b 00b 0b 0b 1b 0b 0b 0b 0b Peripheral HS/FS Suspend 01b 1b 00b 0b 0b 1b 0b 0b 0b 0b Peripheral HS/FS Resume 01b 1b 10b 0b 0b 1b 0b 0b 0b 0b Peripheral LS 10b 1b 00b 0b 0b 0b 1b 0b 0b 0b Peripheral LS Suspend 10b 1b 00b 0b 0b 0b 1b 0b 0b 0b Peripheral LS Resume 10b 1b 10b 0b 0b 0b 1b 0b 0b 0b |
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