SPEAR320S datasheet(111/113 Pages) STMICROELECTRONICS

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SPEAr320S

Revision history

Doc ID 022508 Rev 2

111/113

Revision history

Table 85.

Document revision history

Date

Revision

Changes

5-Apr-2012

Initial release.

27-Sep-2012

Figure 1: SPEAr320S architectural block diagram: Replaced “4 KB

SRAM” by “8 KB SRAM”.

Section 2.2: Internal memories (BootROM/SRAM): Added “Boot

from UART0” and “Boot from Ethernet MII0” to the list of bootstrap

modes.

Section 2.25: System controller (SYSCTR): Replaced “a low-speed

oscillator” by “a crystal oscillator (24 MHz) or a low-frequency

oscillator (32 KHz)” in Doze mode description.

Table 32: Ball sharing during debug: modified the configuration for

pins TEST_2, TEST_3 and TEST_4.

Section 3.4.2: Extended mode: RMII automation networking mode

revised descriptions of each mode.

Section 3.4.5: Boot pins added description of H[7:0] pins Ethernet

MII0 boot and bypass mode.

Updated Figure 3: Hierarchical multiplexing scheme

Added note on I/O direction below Table 13: PL_GPIO / PL_CLK

pins description

Chaged order of columns and added reset states to Table 15:

PL_GPIO/PL_CLK multiplexing scheme and reset states

Added Section 3.5: PL_GPIO and PL_CLK pin sharing for debug and

test modes

Table 8: Debug pins description:

– Replaced “Test configuration ports” by “Debug mode configuration

ports”

– Deleted “For functional mode, they have to be set to zero” for pins

TEST_0 to TEST_4.

– Added a cross-reference.

– Added bypass mode to Table 14: Boot pins description

Section 4.6: Clocking parameters:

– Added Table 40: MCLK oscillator characteristics and new Section :

MCLK generated from a crystal oscillator.

Added Table 42: RTC oscillator characteristics and new Section :

RTC clock generated from an external clock source.Section 4.11:

Reset release:

– Updated the introduction.

– Renamed and updated Figure 7: Cold reset release.

– Added new Figure 8: Warm reset release.

Table 50: Reset timing characteristics: added new row for warm

reset.

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