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STA310 数据表(PDF) 85 Page - STMicroelectronics |
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STA310 数据表(HTML) 85 Page - STMicroelectronics |
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85 / 90 page  85/90 STA310 MLP_STATUS1 MLP status 1 register Address : 0x77 Type: RO Software Reset: NC Hardware Reset: UND Description: This status register contains the channel assignment. MLP_STATUS2 MLP status 2 register Address: 0x78 Type: RO Software Reset: NC Hardware Reset: UND Description: This status register contains the number of sub- streams present in the audio frame. MLP_STATUS3 MLP status 3 register Address:: 0x79 Type: RO Software Reset: NC Hardware Reset: UND Description: This status register contains the sub-stream informa- tion codes.. 9.25 De-emphasis register DEEMPH De-emphasis Address: 0xB5 Type: R/WS Software Reset: NC Hardware Reset: UND Description: This register is used in MPEG, DVD_LPCM or CDDA modes; it is not supported in Dolby Digital. In MPEG and DVD_LPCM modes, its register value is extracted from the bitstream. When the emphasis status changes (by setting bit DEM of the register), an interrupt is generated. In CDDA mode, the register value must be updated by the application. The de-emphasis filter specified here is applied only if bit DEM of the register is set. 9.26 Auxilliary outputs registers VCR_MIX VCR outputs 7654321 0 Reserved CH_ASSIGN[4:0] Bitfield Description CH_ASS IGN[4:0] This gives the channel assignment: See "DVD Specifications for Read-Only Disc", Part 4 AUDIO SPECIFICATIONS, Version 1.0, March 1999, Table C.1-1. 765 43 2 1 0 Reserved NSUBSTR[3:0] 765 4321 0 Reserved SUBSTR_CODE[3:0] Bitfield Description SUBSTR_CODE [3:0] 2-channel decoder: bit0 = ’1’: sub-stream 0 is decoded bit1 = ’1’: a simplified decoder can be used for sub-stream 0 6-channel decoder: bit2 = ’1’: sub-stream 0 is decoded bit3 = ’1’: sub-stream 1 is decoded 7654321 0 reserved D[1:0] Bitfield Description D[1:0] 00: none, 01: 50/15µs, 10: reserved, 11: CCITT J.17 7 6 5 4 321 0 reserved STEREO PRL reserved COPY 3D_VCR |
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