STA310 datasheet(86/90 Pages) STMICROELECTRONICS

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STA310

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Address: 0xAE

Type: R/WS??

Software Reset: NC

Hardware Reset: 0

Description:

Note: 1. To have both "3-D sound" on the "VCR" and "Left/Right"

channels, the setup is:

VCR_MIX = 0x02 and PDEC = 0x40 for SRS process-

ing,

VCR_LDLY

VCR left channel delay

Address: 0xAF

Type: R/WS??

Software Reset: NC

Hardware Reset: 0

Description:

This register contains the VCR left channel delay val-

ue. See note after next register description.

VCR_RDLY

VCR right channel delay

Address: 0xAF

Type: R/WS??

Software Reset: NC

Hardware Reset: 0

Description:

This register contains the VCR right channel delay

value. The values for LEFT_VCR_DELAY and

RIGHT_VCR_DELAY are taken into account only

when register.bit .DLY = ’1’.

9.27 Miscellaneous

BREAKPOINT

To be defined

Address + 0x2B

Type: R/W

Software Reset: NC

Hardware Reset: 0

Description:

This register must be set to 0x08.

CLOCKCMD

To be defined

Address: 0x3A

Type: R/W

Software Reset: NC

Hardware Reset: 0

Description:

This register must be set to 0x00.

Bitfield

Description

3D_VCR

This bit selects "3-D sound" on the VCR

channels using SRS processing

(depending on the PDEC registers and ):

0: Standard sound (disable "3-D sound"),

1: Enable "3-D sound".

COPY

This bit is used to copy "Left/Right"

channels to "VCR" channels:

0: no copy,

1: copy enable.

PRL

This bit enables a "ProLogic downmix" on

the "VCR" channels:

0: Disable,

1: Enable.

STEREO

This bit enables a "2/0 downmix" on the

"VCR" channels:

0: Disable,

1: Enable.

321

LEFT_VCR_DELAY

765

4321

RIGHT_VCR_DELAY

7654321

Reserved

765

4321

Reserved

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