STA310 datasheet(45/90 Pages) STMICROELECTRONICS

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STA310

Address: 0xBF

Type: R/W

Software Reset: 0x01

Hardware Reset: UND

Description:

This register must contain a NDIV value that enables

the

audio

PLL

generate

frequency

ofact*176KHz for the PCMCK.

Default value at soft reset assume:

– Oversampling factor (ofact) = 384. PCMLCK =

384 x SF (where SF is the sampling frequency)

– External crystal provide a clock running at

27MHz

INIT_RAM

STa310 boot Done

Address: 0xFF

Type: RO

Software Reset: 1

Hardware Reset: 0

Description:

This register is used to signal when the STA310 has

finished to boot. After a soft reset or a hardware re-

set, the host processor must wait until INIT_RAM

hold the value “1”.

The host can then start to configure the STA310 ac-

cording to its application.

PLLMASK

PCMCLK mask for half sampling frequency

Address: 0x18

Type: W

Software Reset: NC

Hardware Reset: 0

9.7 Channel delay set-up registers

The six delay setup registers are used to set the rel-

ative delays to the (up to) six loud speaker channels

in order to give the sound effects of, for example, a

large room or to compensate for the listener not being

in the centre of the loud speaker system. The sum of

the delays on the channels must be less than or

equal to 35ms.

The unit for the register delay contents is a group of

16 samples.

Each register value is chosen using the expression:

desired channel delay’*’sampling frequency’/16 sam-

ples and taking care to ensure that the sum of the ’de-

sired channel delays’ is not more than 35ms.

For example, when the sampling frequency is 48kHz,

the sum of the values programmed in the six delay

registers must be less than or equal to:

35 ms * 48 KHz /16 samples = 105.

When only one surround channel is present (in Pro

Logic or other mode), the right surround delay must

be cleared, and the left delay channel is used for both

surround channels.

LDLY

Left channel delay

Address: 0x57

Type: R/W

Software Reset: NC

Hardware Reset: UND

54321

RAM_INIT

HALF_FS

Bitfield

Description

HALF_FS If the incoming bitstream is encoded with

half sampling frequency, the device

generates a PCM clock (for audio DAC)

1: At 256 x half_fs or 384 x half_fs (half_fs

is equal to 24KHz, 22.05KHz, 16KHz).

0: At 256 x fs or 384 x fs (fs is equal to

48KHz, 44.1KHz, 32KHz).

This function is mainly use for DAC

frequency adaptation.

321

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