STA310 datasheet(3/90 Pages) STMICROELECTRONICS

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STA310

LRCLK

Word Clock for the DAC

PCM_OUT0

Data from a Prologic downmix (VCR_L/VCR_R)

PCM_OUT1

Data for the first DAC (Left/Right)

PCM_OUT2

Data for the second DAC (Centre/Sub)

PCM_OUT3

Data for the third DAC (LeftSur/RightSur)

IEC958 Interface (S/PDIF) - One Output Port., One Input Ports.

I958OUT

S/PDIF Signal

SPDP

First differential input of S/P DIF port

SPDN

Second differential input of S/P DIF port

SPDF

External Filter

VDDA

Analog VDD for S/P DIF Input port

GNDA

Analog GND for S/P DIF Input port

STATUS INFORMATION

PCM Related Information

SFREQ

Then high, indicates that the sampling freq. is either 44.1Khz or

22.05Khz.

When low, indicates that the sampling frequency is either 32 Khz,

48 Khz, 24 Khz or 16Khz.

DEEMPH

Indicates if de-emphasis is performed.

Audio Video Synchronization

PTSB

Indicates that a PTS has been detected, active low.

Other Signals

CLK

Master Clock Input Signal.

RESET

I(2)

Reset signal input, active low.

TESTB

I(2)

Reserved pin: to be connected to VDD

SMODE

Reserved pin : to be connected to GND

RS232 Interface

RS232RX

RS232TX

PLLs INTERFACES

CLKOUT

System clock output with programmable division ratio

PLLAF

External Filter For Audio PLL.

STA310 AUDIO DECODER PIN DESCRIPTION (continued)

Pin Number

Name

Type

Function

STA310 数据表(PDF) 3 Page - STMicroelectronics

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