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STA310 数据表(PDF) 42 Page - STMicroelectronics

部件名 STA310
功能描述  62-CH. MULTISTANDARD AUDIO DECODER
PDF  90 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STA310 数据表(HTML) 42 Page - STMicroelectronics

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STA310
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PLLData
Address: 0x11
Type: R/W
Software Reset: NA
Hardware Reset: 0
Description:
Data that must be written (has been read) at (from)
the address specified by PLL_ADD.
PLL_CMD
PLL Command
Address: 0x1D
Type: R/W
Software Reset: NA
Hardware Reset: 0
Description:
PLL_ADD
PLL Address
Address: 0x12
Type: R/W
Software Reset: NA
Hardware Reset: 0
Description:
ENA_AU_FRACPLL
Audio PLL Enable
Address: 0xB5
Type: R/W
Software Reset: 1
Hardware Reset: 0
Description:
This register is used to enable the audio PLL of the
STA310. This register must be always set to “1” after
either a soft or hardware reset.
AU_PLL_FRACL_192
Frac Low Coefficient
Address: 0xB6
76
54
321
0
7654
3
2
1
0
AUPLLCTL
SYSPLLCTL
RWCTL[1:0]
Bitfield
Description
RWCTL [1:0]
Configure PCMCLK source and
direction.
00: No action is performed on the
configuration registers of the level 1
01: Read action of the configuration
registers. During this phase, the
content of a selectable (by PLL_ADD)
register of the level 1 is copied into the
PLL_DATA register.
10: Write action of the configuration
registers. During .this phase, the
content of a selectable (by PLL_ADD)
register of the level 1 is copied into the
PLL_DATA register.
11: Forbidden
SYSPLLCTL
System PLL coefficients transfert
0: No Transfer
1: Transfer the data between the level 1
and the level 2 for the system PLL
AUPLLCTL
Audio PLL coefficient transfert
0: No Transfer
1: Transfer the data between the level 1
and the level 2 for the audio PLL
76
54
321
0
ADDRESS
Value
Address of PLLs configuration registers
Address
2: Disable System PLL
3: System PLL frac Low
4: System PLL frac High
6: System PLL N divider
7: System PLL X divider
8: System PLL M divider
9: System PLL update
10: Disable Audio PLL
11: Audio PLL Frac Low
12: Audio PLL Frac High
14: Audio PLL N divider
15: Audio PLL X divider
16: Audio PLL M divider
17: udio PLL update
765
4
3
2
1
0
ENA_PLL
76
54
321
0
FRACL



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