STA310 datasheet(2/90 Pages) STMICROELECTRONICS

2 / 90 page

STA310

2/90

STA310 AUDIO DECODER PIN DESCRIPTION

Pin Number

Name

Type

Function

CONTROL INTERFACES

IRQB

O (1)

Interrupt Signal (level), active low

SELI2C

I (2)

Selects the Control Interface (when high: serial interface; when

low: parallel interface)

I 2C Control Interface

SDAI2C

I/O (1)

I 2C Serial Data

SCLKI2C

I 2C Clock

MAINI2CADR

I (2)

Determines the slave address

Parallel Control Interface

78 - 79 - 80 - 1

2 - 3 - 6 - 7

D0 - D1 - D2 - D3

D4 - D5 - D6 - D7

I/O

Host Data

12 - 13 - 14 - 15

16 - 18 - 19 - 20

A0 - A1 - A2 - A3

A4 - A5 - A6 - A7

Host Address

DCSB

Chip Select, active low

R/W

Read/Write Selection: read access when high, write access

when low

WAITB

O (3)

Data Acknowledge, active low

DATA INPUT INTERFACE

First Serial Data Interface (I2S)

DSTRB

Clock Input Data, active low

SIN

Serial Input Data

LRCLKIN

Word Clock for the Input

REQ

Handshake for the Data Transfer, aconfigurable by the

SIN_SETUP register

Second Serial Data Interface (I2S)

DSTRB2

Clock Input Data, active low

SIN2

Serial Input Data

LRCLKIN2

Word Clock for the Input

REQ2

Handshake for the Data Transfer, active low

DATA OUTPUT INTERFACES

PCMCLK

I/O

Oversampling Clock input for STA310 when generated externally

DAC Interface

SCLK

Bit Clock for the DAC

STA310 数据表(PDF) 2 Page - STMicroelectronics

STA310 数据表(HTML) 2 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90

数据表下载