STA310 datasheet(54/90 Pages) STMICROELECTRONICS

54 / 90 page

STA310

54/90

Description: These registers indicate which interrupt

occurred. Provided an interrupt is enabled through

the register INTE, if the corresponding bit of INT is

set, the corresponding interrupt has occurred. The

signal IRQ is activated whenever one of the bits of

INT become set. Depending on the nature of the con-

dition, clearing a bit in INT register is performed by ei-

ther reading the MSB of INT register, or by reading

the MSB of the associated condition registers (see

below). This register is reset by software reset.

The table below shows the interrupt nature indicated

by each bit..

Notes: 1. Cleared when a reset occurs or when the MSB of the in-

terrupt register is read

2. Cleared when a reset occurs or when the MSB of the

corresponding register is read. Affected registers are

listed in the following table

3. Only available in STA310 cut 2.0

9.11 Interrupt status registers

SYNC_STATUS

Synchronization status

Address: 0x40

Type: RO

Software Reset: UND

Hardware Reset: UND

Bit

Numer

Name

Condition Signalled

SYN

Change in Synchronization Status (1)

HDR

Valid Header Registered (1)

ERR

Error Detected (1)

SFR

Sampling frequency changed (2)

DEM

De-emphasis Changed (2)

BOF

First Bit of New Frame at Output

Stage (2)

PTS

First Bit of New Frame with PTS at

Output Stage (2)

ANC

Not implemented

PCM

PCM Output Underflow (2)

FBF

Frame Buffer Full: The frame buffer

memory contains 2 frames: one

decoded, and one parsed for next

decoding

FBE

Frame Buffer Empty: The frame

buffer memory contains 1 frame

which begins to be decoded. The

next frame begins to be parsed

FIO

FIFO Input has Overflowed (2)

RST(3)

The STA310 has detected a change

in the incoming audio format. The

soft Reset produce must be applied

and the device must be re-initialized

according to the new audio format

detected. Registers DECODESEL

(0x4d) and STREAMSEL (0x4c)

contain the new audio format (1)

LCK(3)

A break has occurred in the S/PDIF

stream causing the internal S/PDIF

PLL to get unlocked. The soft reset

procedure must be applied and the

device must be re-initialized

according to the current audio format

decoding contained in the registers

DECODESEL (0x4d) and

SRTREAMSEL (0x4c). (1)

USD

Reserved

TBD

Reserved

Address

Name

0x0F

ERROR

0x40

SYNCSTATUS

0x41

ANCCOUNT

0x42

HEAD 4

0x46

PTS [32]

765

4321

PAC

FRA

Bit

Numer

Name

Condition Signalled

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