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STA310 数据表(PDF) 47 Page - STMicroelectronics

部件名 STA310
功能描述  62-CH. MULTISTANDARD AUDIO DECODER
PDF  90 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STA310 数据表(HTML) 47 Page - STMicroelectronics

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STA310
RVDLY
Right VCR channel delay
Address: 0xB0
Type: R/W
Software Reset: NC
Hardware Reset: UND
Description:
Delay on right VCR channel, expressed in number of
group of 16 samples. RSDLY = delay (ms) * Fs (kHz)
/ 16.
When only one VCR channel is used, this register
must be reset at initialization.
UPDATE
PCM delay update
Address: 0x5D
Type: R/W
Software Reset: 0
Hardware Reset 0
Description:
9.8 SPDIF output set-up
SPDIF_CMD
SPDIF control
Address: 0x5E
Type: R/W
Software Reset: NC
Hardware Reset: UND
This register controls the SPDIF mode:
Description:
SPDIF_CAT
Category code
76
54
321
0
76
54
321
0
TM
DLY
Bitfield
Description
DLY
This bit must be set to 1 to force the DSP to
update its delays values (read from the audio
delay registers).
0: Delay values held in the audio delay
registers are NOT updated in the DSP
(i.e. the DSP will keep the delay values set
previously)
1: The delay values held in the audio delay
registers are updated in the DSP (i.e. the
DSP will use the new values). This bit is
automatically reset to zero after it the update
has been carried out.
TM
Set to “0”
76
5
4
3
2
1
0
AUX
reserved
SPDIF_MODE[1:0]
Bitfield
Description
SPDIF_MODE[1:0]
AUX = ’0’
00: OFF, the IEC60958 is not working and the output line is idle,
01: MUTE, the outputs are PCM null data,
10: PCM, the outputs are PCM data and only the Left/Right channels are transmitted,
11: EMC, in this "encoded" mode the compressed bitstream is transmitted in IEC61937
standard.
SPDIF_MODE[1:0]
AUX = ’1’
10: PCM, the outputs are PCM data and only the "VCR" channels are transmitted.
All other values are reserved.
76
543210
CATCODE



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