STA310 datasheet(40/90 Pages) STMICROELECTRONICS

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STA310

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Address : 0x0E

Type: WO

Software Reset: NA

Hardware Reset: NA

Description:

Data can be fed into the STa310 by using this register

instead of the dedicated interface. there is no need to

byte align the bitstream when using this register.

9.5 PCM CONFIGURATION RESISTERS

PCMDIVIDER

Divider for PCM clock

Address : 0x54

Type: R/W

Software Reset: UND

Hardware Reset: UND

Description:

The PCM divider must be set according to the formu-

la below, where DAC_SCLK is the bit clock for the

DAC. When Div is set to 0, DAC_SCLK is equal to

DAC_PCMCLK:

Div = (DAC_PCMCLK/ (2 x DAC_SCLK)) -1

When the internal PLL is used, DAC_PCMCLK=384

x fs or 256 x fs. If DAC_PCMCLK = 384 x fs, the for-

mula becomes:

Div = (192 x Fs/DAC_SCLK) -1

If DAC_SCLK is 32 x Fs (common case with the 16

bit DAC), Div must be set to 5.

PCMCONF

PCM configuration

Address: 0x55

Type: R/W

Software Reset: NC

Hardware Reset: UND

Description:

PCMCROSS

321

PCM divider value

Mode description

DAC_PCMCLK = 384Fs,

DAC is 16-bit mode

DAC_PCMLK = 256 Fs,

DAC is 16-bit mode

DAC_PCMLK = 384 Fs,

DAC is 32-bit mode

DAC_PCMLK = 256 Fs,

DAC is 32-bit mode

ODR DIF

INV

FOR

SCL

PREC[1:0]

Bitfield

Description

ORD

PCM Order: This bit is significant only

when in 16-bit mode. When set, LSB

is sent first. When reset, MSB is sent

first.

DIF

PCM_DIFF: This bit is not significant

in 16-bit. When set, indicates that the

bits are not right-padded in the slot.

When reset, Ii is right padded.

INV

INV_LRCLK: When set the polarty of

LRCLK is inverted: Left channel is

output when LRCLK is high.

When reset, the polarity of LRCLK is

such that the left channel is outout

when LRCLK is low.

FOR

FORMAT: This bit selects the data

output format: When set, the Sony

format is chosen. When reset 0 the

format is IS format.

SCL

INV_SCLK: When set, the polarity of

SCLK is inverted, the PCM outputs

and LRCLK will be stable for the

DACs on the falling edge of SCLK.

When reset, PCM outputs and LRCLK

are stable on the rising edge of SCLK.

PREC[1:0]

PCM Precision

0: 16 bit mode (16 slots)

1: 18 bit mode (32 slots)

2: 20 bit mode (32 slots)

3: 24 bit mode (32 slots)

VCR

CLR[1:0]

CSW[1:0]

LRS[1:0]

PCM divider value

Mode description

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