STA310 datasheet(60/90 Pages) STMICROELECTRONICS

60 / 90 page

STA310

60/90

When it has detected (SYNC_LOCK+1) sync words,

it sends the data to the decoder.

9.14 Post decoding and pro logic registers

PDEC1

Post decoder register

Address: 0x62

Type: R/W

Software Reset: NC

Hardware Reset: UND

Description:

This register controls the post decoder operations.

PL_AB

Pro Logic auto balance

Address : 0x64

Type: R/W

Software Reset: NC

Hardware Reset: UND

Description:

PL_DWNX

Pro Logic Decoder Downmix

Address : 0x65

Type: R/W

Software Reset: NC

Hardware Reset: UND

Description:

Prologic decoder support only 4 sampling frequen-

cies: 48KHz, 44.1KHz, 32KHz, 22.05KHz.

If we active prologic with sampling frequency differ-

ent from those frequencies, the decoder will be auto-

matically disable the prologic call.

OCFG

Output Configuration

Address: 0x66

VMAX

DEM DCF DB PVIRT MPEG_DR PL

Bitfield

Description

When high Pro Logic decoding is forced,

when low the ProLogic decoder is

automatically enabled when the stream

contains the info that it is ProLogic

encoded

MPEG_DR When high enable MPEG dynamic range.

When high the "double stereo" procedure

is enabled. Double stereo is a copy of

Left/Right channels on to Left/Right

surround channels in order to have a

pseudo 5 -channel decoder effect.

DCF

When set the DC filter is activated.. When

reset, it is disabled.

DEM

When set the de-emphasis filter is

activated.. When reset, it is disabled.

543

PL_WS

PL_AB

Bitfield

Description

PL_AB

When high, select the auto-balance

function (used to track out gin

mismatches between Lt and Rt).When

low, disable the autobalance function

PL_WS

When high, enable Wide Surround mode.

The wide surround option is provided for

users who plan to do further post-

processing of the Pro Logic outputs, and

want to fold the lowpass filtering of the

surround channel into their downstream

processing Lowpass filtering and B-type

shelf filtering are both disabled. When

low, disable ide surround mode.

7654

LFE_BYP

PL_DWNX[2:0]

Bitfield

Description

PL_DWNX

[2:0]

0,1,2: Pro Logic disabled

3: 3/0 (L, R, C) three stereo

4: 2/1 (L, R, Ls) phantom

5: 3/1 (L, C, R, Ls)

6: 2/2 (L, R, Ls, Rs) phantom

7: 3/2 (L, C, R, S, S)

LFE_BYP

0: LFE channel is clear

1: LFE channel is bypassed

54321

LFE_BYP BOOST

OCFG[2:0]

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