STA310 datasheet(32/90 Pages) STMICROELECTRONICS

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STA310

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AUDIO/VIDEO SYNCHRONIZATION

8.1 Presentation time stamp detection

8.1.0.1 PTS Signal

This signal, PTS, is used to signal the detection of a Presentation Time Stamp in a stream, for audio/video syn-

chronization. When a PTS is detected, the signal PTS goes low during one LRCLK period. It is generated while

the PCM are output, so to enable the use of an external counter to synchronize the STA310 with a video decod-

er.

The signal is activated, even if PTS interrupt is not enabled.

8.1.1 PTS interrupt

When enabled through the INTE register, the interrupt PTS is generated when a PTS is detected. The interrupt

is signalled on the IRQ output, which goes low. The IRQ signal is de-activated once the PTS bit has been

cleared in INT register by reading the PTS Most Significant Bit.

8.1.2 PTS interrupt and signal relative timings

The IRQ configured as PTS interrupt is output before the PTS signal. The PTS signal is activated at last one

period of LRCLK after the IRQ signal.

8.2 Frames skip capability

When the audio decoder is late compared to the video decoder, the decoder is able to skip frames. Writing 1 in

the SKIP_FRAME register makes the decoder ignore the next incoming frame. Once skipping the frame, it con-

tinues to decode the stream, and the SKIP_FRAME register is automatically reset.

8.3 Frames repeat capability

When the audio decoder is ahead of the video decoder, the decoder can repeat frames. Writing 1 in the

REPEAT_FRAME register makes the decoder repeat the current frame. Once repeating the frame, the chip

plays the next incoming frame, and the REPEAT_FRAME register is reset.

9.1 Introduction

The STA310 device contains 256 registers.

Two types of registers exist:

- From address 0x00 to 0x3F, the registers are real registers that can be initialized after reset.

- From address 0x40 to 0x100, they are memory locations. This means that the registers located at the

address 0x40 to 0x100 can have different meanings and usage according to the mode in which the

device operates.

Be careful that they can not be hardware reset: they contain undefined values at reset and require to

be initialized after each hardware reset.

In this document, only the user registers are described.

The undocumented registers are reserved. These registers must never be accessed (neither in Read nor in

Write mode).

The Read only registers must never be written

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