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STA310

Address: 0x56

Type: R/W

Software Reset: NC

Hardware Reset: UND

Description:

The PCMCROSS register only acts if bit PFC of reg-

ister SPDIF_DTDI is set.

9.6 PDAC and PLL configuration registers

SFREQ

Sampling frequency

Address: 0x05

Type: R/WS

Software Reset: NC

Hardware Reset: 0

Description:

This status register holds the code of the current

sampling frequency. If the audio stream is encoded

(Dolby Digital, MPEG) or packetized (DVD_LPCM),

the sampling frequency is automatically read in the

audio stream and written into this register by the au-

dio DSP. The register is automatically updated by the

DSP when it performs a down-sampling (for exam-

ple, 96kHz to 48kHz).

The DSP resets SFREQ to 0.

For PCM stream or CDDA, this register is written to

by the application. The value in SFREQ corresponds

to the following frequencies:.

PLLCTRL

PLL Control

Address: 0x12

Type: R/W

Software Reset: NA

Hardware Reset: 0x19

Description:

PLL_DATA

Bitfield

Description

LRS[1:0]

Cross left and right surround.

CSW[1:0]

Cross centre and subwoofer.

CLR[1:0]

Cross left and right channels.

00: Left channel is mapped on the left

output, Right channel is mapped on the

Right output.

01: Left channel is duplicated on both

outputs.

10: Right channel is duplicated on both

outputs.

11: Right channel and Left channel are

toggled.

VCR[1:0]

These 2 bits manage the VCR outputs.

321

(KHz)

46 44.1 32

96 88.2 64

24 22.05

Value

(KHz)

12 11.025

192 176.4 128 -

Value 10 11 12

15 16

18 19

765

SYSCLSCK[1..0]

OCLK[2..0]

Bitfield Value

Description

OCLK

[2:0]

Configure PCMCLK

source and direction

PCMCLK pad

direction

-01

Audio master Clock

from PCMLCK pad.

Input

011

Audio master Clock

from internal audio

PLL

Input

111

Audio master Clock

from internal S/PDIF

receiver

Input

-00

Forbidden

010

Audio master Clock

from internal audio

PLL

Output

110

Audio master Clock

from internal S/PDIF

receiver

Output

SYSCLC

K[1:0]

System Clock from CLK pad

Output

System Clock from CLK pad divided

by 2

System Clock from internal system

PLL

System Clock from internal system

PLL divided by 2

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