STA310 datasheet(9/90 Pages) STMICROELECTRONICS

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STA310

- The signal WAIT. This signal is always driven low in response to the DCSB assertion.

The timing diagrams for the parallel control interface are given in

Electrical specifications on page 5.

3.4 I2C control interface

When the pin SELI2C is high, the chip is controlled through the I²C interface. The I²C unit works at up to 400kHz

in slave mode with 7-bit addressing.

- The Pin MAINI2CADR selects the device address. When MAINI2CADR is high the slave address is

0x5C, when low the device address is equal to the value on the address bus (A0...A6).

- The pin SDAI2C is the serial data line.

- The pin SCLKI2C is the serial clock.

The I²C Bus standard does not specify sub-addressing. There are thus potentially multiple ways to implement

it. Any implementation that respects the standard is of course legal but a particular implementation is used by

many companies. The following paragraphs describe this implementation.

3.4.1 Protocol description

For write accesses only, the first data which follows the slave address is always the sub-address.

This is the one and only way to declare the sub-address. It should be noticed that the sub-address is implement-

ed as a standard data on the I²C Bus protocol point of view. It is a sub-address because the slave knows that it

must load its address pointer with the first data sent by the master.

See in the Appendix X.x for I2C message format examples.

3.5 Decoding process

The decoding process in the STA310 is done in several stages:

- Parsing,

- Main decoding,

- Post decoding,

- Bass redirection,

- Volume and Balance control.

Each of the stages can be activated or bypassed according to the configuration registers.

Parsing

The bitstream parsing (performed by the input processor) is in charge of discarding all the non audio information

in order to transmit to the next stage (the circular frame buffer) only the audio elementary stream (AC3, MPEG1/

2, LPCM, PCM, DVD Audio).

The parsing stage operates in two phases: the packet parser unpacks the stream, the audio parser checks the

syntax of the bitstream.

Main Decoding

The input of this stage is an elementary stream, the outputs are decoded samples. The number of output chan-

nels is defined by the downmix register (1 channel up to 6 channels). For details, please refer to the description

of the register.

The decoding formats currently supported are AC3, MPEG1 layers I and II, MPEG2 layer II, LPCM. It is neces-

sary to select the appropriate stream format by configuring the registers STREAMSEL and DECODESEL before

running the decoder.

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