STA310 datasheet(13/90 Pages) STMICROELECTRONICS

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STA310

4.2.2.3 Word clock LRCLK

The frequency of LRCLK is given by:

- Flrclk = Fsclk/32; for 16 bit PCM output,

- Flrclk = Fsclk/64; for 18, 20 or 24 bits PCM output.

No special configuration is required. The polarity can be changed in the register PCMCONF, by setting up the

field INV as needed.

4.3 Decoding states

There are two different decoder states: Idle state and decode state (see <Blue HT>Figure 3). To change states,

Figure 5. Decoding States

Idle Mode

This is the state entered after a hardware or software reset. In this state, the embedded DSP does not decode,

i.e. no data are processed. The chip is waiting for the RUN command, and during this state all configuration

registers must be initialized. In this state, even if the chip is not processing data, the DACs clocks can be output,

which enables to setup the external DACs. Once the PCMCLK, SCLK and LRCLK clocks are configured, it is-

possible to output them by setting the MUTE register.I

Table 2. Idle mode. play and mute commands effects

Note: 1. The PLAY command has no effect in this state as the decoder is not running. It can however be sent and it will be taken into account

as soon as the decoder enters the decode state.

Decode Mode

This state is entered after the RUN command has been sent (i.e. RUN register = 1). In this mode, the data are

processed. The decoder can play sound, or mute the outputs, by using the PLAY and MUTE registers:

- To decode streams, the PLAY register must be set. When decoding, the sound will be sent to outputs

if the MUTE register is reset. The outputs are muted if the MUTE register is set.

- To stop decoding, the PLAY register should be reset. Resuming decoding is performed by writing

PLAY to 1 again

Play

Mute

Clock (SCLK, LRCLK) State

PCM Output

Not running

Running

Idle mode

Init mode

Decode mode

Time

Soft reset

Run command

Decoder ready to play sample

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