ST7MC1 datasheet(200/308 Pages) STMICROELECTRONICS

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ST7MC1/ST7MC2

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MOTOR CONTROLLER (Cont’d)

10.6.10.2 Functional Description

The 3 PWM signals are generated using a free-

running 12-bit PWM Counter and three 13-bit

Compare registers for phase U, V and W: MCM-

PU, MCMPV and MCMPW registers.

A fourth 12-bit register is needed to set-up the

PWM carrier frequency: MCMP0 register.

Each of these compare registers is buffered with a

preload register. Transfer from preload to active

registers is done synchronously with PWM counter

underflow or overflow depending on configuration.

This allows to write compare values without risks

of spurious PWM transitions.

The block diagram of the PWM generator is shown

on Figure 117.

10.6.10.3 Prescaler

The 12-bit PWM Counter clock is supplied through

a 3-bit prescaler to allow the generation of lower

PWM carrier frequencies. It divides Fmtc by 1, 2, 3,

..., 8 to get Fmtc-pwm.

This prescaler is accessed through three bits

PCP[2:0] in MPCR register; this register is buff-

ered: the new value is taken into account after a

PWM update event.

10.6.10.4 PWM Operating mode

The PWM generator can work in center-aligned or

edge-aligned mode depending on the CMS bit set-

ting in the MPCR register.

Figure 118 shows the corresponding counting se-

quence .

It offers also an 8-bit mode to get a full 8-bit range

with a single compare register write access by set-

ting the PMS bit in MPCR register.

The comparisons described here are performed

between the PWM Counter value extended to 13

bits and the 13-bit Compare register. Having a

compare range greater than the counter range is

mandatory to get a full PWM range (i.e. up to

100% modulation). This principle is maintained for

8-bit PWM operations.

■ Center-aligned Mode (CMS bit = 1)

In this operating mode, the PWM Counter counts

up to the value loaded in the 12-bit Compare 0 reg-

ister then counts down until it reaches zero and re-

starts counting up.

The PWM signals are set to ‘0’ when the PWM

Counter reaches, in up-counting, the correspond-

ing 13-bit Compare register value and they are set

to ‘1’ when the PWM Counter reaches the 13-bit

Compare value again in down-counting.

Figure 118. Counting sequence in center-aligned and edge-aligned mode

center-aligned

mode

....1516

15....

edge-aligned

mode

.....

T = PWM period, Value of 12-bit Compare 0 Register= 16

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