ST7MC1 datasheet(206/308 Pages) STMICROELECTRONICS

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ST7MC1/ST7MC2

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MOTOR CONTROLLER (Cont’d)

10.6.13 Register Description

TIMER COUNTER REGISTER (MTIM)

Read /Write

Reset Value: 0000 0000 (00h)

Bits 7:0 = T[7:0]: MTIM Counter Value.

These bits contain the current value of the 8-bit up

counter. In Speed Measurement Mode, when us-

ing Encoder sensor and MTIM captures triggered

by SW (refer to Figure 102) a read access to MTIM

TIMER COUNTER REGISTER LSB (MTIML)

Read /Write

Reset Value: 0000 0000 (00h)

Bits 7:0 = TL[7:0]: MTIM Counter Value LSB.

These bits contain the current value of the least

significant byte of the MTIM up counter, when

used in Speed Measurement Mode (i.e. as a 16-bit

timer)

CAPTURE Zn-1 REGISTER (MZPRV)

Read /Write

Reset Value: 0000 0000 (00h)

Bits 7:0 = ZP[7:0]: Previous Z Value or Speed

capture LSB.

These bits contain the previous captured BEMF

value (ZN-1) in Switched and Autoswitched mode

or the LSB of the captured value of the

[MTIM:MTIML] registers in Speed Sensor Mode.

CAPTURE Zn REGISTER (MZREG)

Read/Write

Reset Value: 0000 0000 (00h)

Bits 7:0 = ZC[7:0]: Current Z Value or Speed cap-

ture MSB.

These bits contain the current captured BEMF val-

ue (ZN) in Switched and Autoswitched mode or the

MSB of the captured value of the [MTIM:MTIML]

registers in Speed Sensor Mode. A read access to

MZREG in this case disable the Speed captures

up to MZPRV reading (refer to Section 10.6.7.5

Speed Measurement Mode on page 179).

COMPARE Cn+1 REGISTER (MCOMP)

Read/Write

Reset Value: 0000 0000 (00h)

Bits 7:0 = DC[7:0]: Next Compare Value.

These bits contain the compare value for the next

commutation (CN+1).

DEMAGNETIZATION REGISTER (MDREG)

Read/Write

Reset Value: 0000 0000 (00h)

Bits 7:0 = DN[7:0]: D Value.

These bits contain the compare value for simulat-

ed demagnetization (DN) and the captured value

for hardware demagnetization (DH) in Switched

and Autoswitched mode.

In Speed Sensor Mode, the register contains the

value used for comparison with MTIM registers to

generate a Speed Error event.

TL7

TL6

TL5

TL4

TL3

TL2

TL1

TL0

ZP7

ZP6

ZP5

ZP4

ZP3

ZP2

ZP1

ZP0

ZC7

ZC6

ZC5

ZC4

ZC3

ZC2

ZC1

ZC0

DC7

DC6

DC5

DC4

DC3

DC2

DC1

DC0

DN7

DN6

DN5

DN4

DN3

DN2

DN1

DN0

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