ST7MC1 datasheet(205/308 Pages) STMICROELECTRONICS

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ST7MC1/ST7MC2

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MOTOR CONTROLLER (Cont’d)

10.6.10.7 Timer Re-synchronisation

The 12-bit timer can be re-synchronized by a sim-

ple write access with FFh value in the MISR regis-

ter. Re-synchronization means that the 12-bit

counter is reset and all the compare preload regis-

ters MCP0, MCPU, MCPV, MCPW are transferred

to the active registers.

To re-synchronize the 12-bit timer properly , the

following procedure must be applied:

– 1. Load the new values in the preload compare

registers

– 2. Load FFh value in the MISR register (this will

reset the counter and transfer the compare

preload registers in the active registers: U event)

– 3. Reset the PUI flag by loading 7Fh in the MISR

Note: Loading FFh value in the MISR register will

have no effect on any other flag than the PUI flag

and will generate a PWM update interrupt if the

PUM bit is set.

Warning: In switched mode (SWA bit is reset), the

procedure is the same and loading FFh in the

MISR register will have no effect on flags except

on the PUI flag. As a consequence, it is recom-

mended to avoid setting RMI and RPI flags at the

same time in switched mode because none of

them will be taken into account.

10.6.10.8 PWM generator initialization and

start-up

The three-phase generator counter stays in reset

state (i.e. stopped and equal to 0), as long as MTC

peripheral clock is disabled (CKE = 0).

Setting the CKE bit has two actions on the PWM

generator:

■ It starts the PWM counter

■ It forces the update of all registers with preload

registers transferred on U update event, i.e.

MREP, MPCR, MCMP0, MCMPU, MCMPV,

MCMPW (in 12-bit mode, both MCMPxL and

MCMPxH must have been written, following the

mandatory LSB/MSB sequence, before setting

CKE bit). It consequently generates a U

interrupt.

10.6.11 Low Power Modes

Before executing a HALT or WFI instruction, soft-

ware must stop the motor, and may choose to put

the outputs in high impedance.

10.6.12 Interrupts

The MTC interrupt events are connected to the

three interrupt vectors (see Interrupts chapter).

They generate an interrupt if the corresponding

Enable Control Bit is set and the interrupt mask in

the CC register is reset (RIM instruction).

Mode

Description

WAIT

No effect on MTC interface.

MTC interrupts exit from Wait mode.

HALT

MTC registers are frozen.

In Halt mode, the MTC interface is in-

active. The MTC interface becomes

operational again when the MCU is

woken up by an interrupt with “exit

from Halt mode” capability.

Interrupt Event

Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

Ratio increment

RPI

RIM

Yes

Ratio decrement

RMI

Yes

Speed Error

SEI

SEM

Yes

Emergency Stop

EIM

Yes

Current Limitation

CLI

CLIM

Yes

BEMF Zero-Crossing

ZIM

Yes

End of Demagnetization

DIM

Yes

Commutation or

Capture

CIM

Yes

PWM Update

PUI

PUM

Yes

Sampling Out

SOI

SOM

Yes

Not

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