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LSM6DSL 数据表(PDF) 57 Page - STMicroelectronics |
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LSM6DSL 数据表(HTML) 57 Page - STMicroelectronics |
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57 / 113 page  DocID028475 Rev 5 57/113 LSM6DSL Register description 113 9.9 DRDY_PULSE_CFG_G (0Bh) DataReady configuration register (r/w). Table 42. DRDY_PULSE_CFG_G register Table 43. DRDY_PULSE_CFG_G register description 9.10 INT1_CTRL (0Dh) INT1 pad control register (r/w). Each bit in this register enables a signal to be carried through INT1. The pad’s output will supply the OR combination of the selected signals. Table 44. INT1_CTRL register Table 45. INT1_CTRL register description DRDY_ PULSED 0(1) 1. This bit must be set to ‘0’ for the correct operation of the device. 0(1) 0(1) 0(1) 0(1) 0(1) INT2_ WRIST_TILT DRDY_PULSED Enable pulsed DataReady mode. Default value: 0 (0: DataReady latched mode. Returns to 0 only after output data have been read; 1: DataReady pulsed mode. The DataReady pulses are 75 μs long.) INT2_ WRIST_TILT Wrist tilt interrupt on INT2 pad. Default value: 0 (0: disabled; 1: enabled) INT1_STEP_ DETECTOR INT1_SIGN _MOT INT1_FULL _FLAG INT1_ FIFO_OVR INT1_ FTH INT1_ BOOT INT1_ DRDY_G INT1_ DRDY_XL INT1_ STEP_ DETECTOR Pedometer step recognition interrupt enable on INT1 pad. Default value: 0 (0: disabled; 1: enabled) INT1_SIGN_MOT Significant motion interrupt enable on INT1 pad. Default value: 0 (0: disabled; 1: enabled) INT1_FULL_FLAG FIFO full flag interrupt enable on INT1 pad. Default value: 0 (0: disabled; 1: enabled) INT1_FIFO_OVR FIFO overrun interrupt on INT1 pad. Default value: 0 (0: disabled; 1: enabled) INT1_FTH FIFO threshold interrupt on INT1 pad. Default value: 0 (0: disabled; 1: enabled) INT1_ BOOT Boot status available on INT1 pad. Default value: 0 (0: disabled; 1: enabled) INT1_DRDY_G Gyroscope Data Ready on INT1 pad. Default value: 0 (0: disabled; 1: enabled) INT1_DRDY_XL Accelerometer Data Ready on INT1 pad. Default value: 0 (0: disabled; 1: enabled) |
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