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LSM6DSL 数据表(PDF) 80 Page - STMicroelectronics |
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LSM6DSL 数据表(HTML) 80 Page - STMicroelectronics |
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80 / 113 page  Register description LSM6DSL 80/113 DocID028475 Rev 5 9.59 TIMESTAMP0_REG (40h) Timestamp first byte data output register (r). The value is expressed as a 24-bit word and the bit resolution is defined by setting the value in WAKE_UP_DUR (5Ch). 9.60 TIMESTAMP1_REG (41h) Timestamp second byte data output register (r). The value is expressed as a 24-bit word and the bit resolution is defined by setting value in WAKE_UP_DUR (5Ch). 9.61 TIMESTAMP2_REG (42h) Timestamp third byte data output register (r/w). The value is expressed as a 24-bit word and the bit resolution is defined by setting the value in WAKE_UP_DUR (5Ch). To reset the timer, the AAh value has to be stored in this register. Table 150. TIMESTAMP0_REG register TIMESTA MP0_7 TIMESTA MP0_6 TIMESTA MP0_5 TIMESTA MP0_4 TIMESTA MP0_3 TIMESTA MP0_2 TIMESTA MP0_1 TIMESTA MP0_0 Table 151. TIMESTAMP0_REG register description TIMESTAMP0_[7:0] TIMESTAMP first byte data output Table 152. TIMESTAMP1_REG register TIMESTA MP1_7 TIMESTA MP1_6 TIMESTA MP1_5 TIMESTA MP1_4 TIMESTA MP1_3 TIMESTA MP1_2 TIMESTA MP1_1 TIMESTA MP1_0 Table 153. TIMESTAMP1_REG register description TIMESTAMP1_[7:0] TIMESTAMP second byte data output Table 154. TIMESTAMP2_REG register TIMESTA MP2_7 TIMESTA MP2_6 TIMESTA MP2_5 TIMESTA MP2_4 TIMESTA MP2_3 TIMESTA MP2_2 TIMESTA MP2_1 TIMESTA MP2_0 Table 155. TIMESTAMP2_REG register description TIMESTAMP2_[7:0] TIMESTAMP third byte data output |
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