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ST7MC1K2-Auto 数据表(PDF) 55 Page - STMicroelectronics |
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ST7MC1K2-Auto 数据表(HTML) 55 Page - STMicroelectronics |
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55 / 371 page  Obsolete Product(s) - Obsolete Product(s) ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto Supply, reset and clock 55/371 Figure 15. Main clock controller (MCC/RTC) block diagram 6.6.5 Low power modes DIV 2, 4, 8, 16 MCC/RTC interrupt SMS DIV128 CP0 TB1 TB0 OIE OIF CPU clock to MCCSR RTC counter CPU and peripherals fOSC2 fCPU MCO MCO BC1 BC0 MCCBCR Beep generator Beep signal To motor control peripheral fMTC (and to MTC peripheral) DIV 2, 4, 8, 16 DIV 2 fCLK DIV 2 fADC Table 11. Effect of low power modes on MCC/RTC Mode Description Wait No effect on MCC/RTC peripheral. MCC/RTC interrupt cause the device to exit from Wait mode. Active Halt No effect on MCC/RTC counter (OIE bit is set), the registers are frozen. MCC/RTC interrupt cause the device to exit from Active Halt mode. Halt MCC/RTC counter and registers are frozen. MCC/RTC operation resumes when the MCU is woken up by an interrupt with ‘exit from HALT’ capability. Obsolete Product(s) - Obsolete Product(s) |
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