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ST7MC1K2-Auto 数据表(PDF) 58 Page - STMicroelectronics |
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ST7MC1K2-Auto 数据表(HTML) 58 Page - STMicroelectronics |
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58 / 371 page  Obsolete Product(s) - Obsolete Product(s) Supply, reset and clock management ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, 58/371 6.6.8 MCC beep control register (MCCBCR) 6.6.9 Main clock controller register map and reset values MCCBCR Reset value: 0000 0000 (00h) 76543 210 Reserved ADSTS ADC IE BC[1:0] - R/W R/W R/W Table 14. MCCBCR register description Bit Name Function 7:4 - Reserved, must be kept cleared 3ADSTS A/D converter sample time stretch This bit is set and cleared by software to enable or disable the A/D converter sample time stretch feature. 0: AD sample time stretch disabled (for standard impedance analog inputs) 1: AD sample time stretch enabled (for high impedance analog inputs) 2ADC IE A/D converter interrupt enable This bit is set and cleared by software to enable or disable the A/D converter interrupt. 0: AD Interrupt disabled 1: AD Interrupt enabled 1:0 BC[1:0] Beep control These 2 bits select the PF1 pin beep capability: 00: Beep mode (with fOSC2 =8 MHz) =off 01: Beep mode (with fOSC2 = 8 MHz) = .~2 kHz (output beep signal ~50% duty cycle) 10: Beep mode (with fOSC2 = 8 MHz) = .~1 kHz (output beep signal ~50% duty cycle) 11: Beep mode (with fOSC2 = 8 MHz) = .~500 Hz (output beep signal ~50% duty cycle) The beep output signal is available in Active Halt mode but has to be disabled to reduce the consumption. Table 15. Main clock controller register map and reset values Address (Hex.) Register label 7 6 5 4 3 2 1 0 0040h SICSR, page0 reset value PAGE 0 VDIE 0 VDF 0 LVDRF x0 CFIE 0 CSSD 0 WDGRF x 0040h SICSR, page1 reset value PAGE 00 VCOEN 0 LOCK x PLLEN 00 CKSEL 00 002Ch MCCSR reset value MCO 0 CP1 0 CP0 0 SMS 0 TB1 0 TB0 0 OIE 0 OIF 0 002Dh MCCBCR reset value 0 0 0 0 ADSTS 0 ADCIE 0 BC1 0 BC0 0 Obsolete Product(s) - Obsolete Product(s) |
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