ST7MC1K2-Auto datasheet(17/371 Pages) STMICROELECTRONICS

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Figure 99.

Step ratio bits decoding and accuracy results and BEMF sampling rate . . . . . . . . . . . . . 225

Figure 100. Tachogenerator period acquisition using MTIM timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

Figure 101. Encoder clock frequency measure using MTIM timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

Figure 102. Hall sensor period acquisition using MTIM timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

Figure 103. Overview of MTIM timer in speed measurement mode . . . . . . . . . . . . . . . . . . . . . . . . . . 230

Figure 104. Auto-updated prescaler functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

Figure 105. Prescaler auto-change example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

Figure 106. Current window and feedback filters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

Figure 107. Current feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

Figure 108. Sampling clock generation block(1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

Figure 109. Channel manager block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

Figure 110. PWM application in voltage or current sensorless mode (see Table 133) . . . . . . . . . . . . 244

Figure 111. PWM application in voltage or current sensor mode (see Table 134) . . . . . . . . . . . . . . . 245

Figure 112. Deadtime waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

Figure 113. Deadtime waveform with delay greater than the negative PWM pulse. . . . . . . . . . . . . . . 246

Figure 114. Deadtime waveform with delay greater than the positive PWM pulse . . . . . . . . . . . . . . . 246

Figure 115. Channel manager output block diagram with PWM generator delivering three PWM

signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

Figure 116. Channel manager output block diagram with PWM generator delivering 1 PWM signal . 250

Figure 117. Complementary PWM signals with chopping frequency on high and low side drivers . . . 252

Figure 118. PWM generator block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

Figure 119. Counting sequence in center-aligned and edge-aligned mode . . . . . . . . . . . . . . . . . . . . 254

Figure 120. Center-aligned PWM waveforms (compare 0 register = 8). . . . . . . . . . . . . . . . . . . . . . . . 255

Figure 121. Edge-aligned PWM waveforms (compare 0 register = 8) . . . . . . . . . . . . . . . . . . . . . . . . . 256

Figure 122. Comparison between 12-bit and 8-bit PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

Figure 123. Update rate examples depending on mode and MREP register setting . . . . . . . . . . . . . . 258

Figure 124. General view of the MTC for PM BLDC motor control . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

Figure 125. General view of the MTC configured for Induction motor control (proposal) . . . . . . . . . . 290

Figure 126. Page mapping for motor control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

Figure 127. Normal op-amp operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

Figure 128. ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298

Figure 129. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312

Figure 130. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

Figure 131. fCPU max versus VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

Figure 132. Typical IDD in RUN vs fCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

Figure 133. Typical IDD in SLOW vs fCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318

Figure 134. Typical IDD in Wait vs fCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318

Figure 135. Typical IDD in Slow Wait vs fCPU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

Figure 136. Typical application with an external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

Figure 137. Typical application with a crystal or ceramic resonator. . . . . . . . . . . . . . . . . . . . . . . . . . . 322

Figure 138. PLL and clock detector signal start up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324

Figure 139. Two typical applications with unused I/O pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

Figure 140. Typical IPU vs. VDD with VIN =VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

Figure 141. Typical RPU vs. VDD with VIN =VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

Figure 142. Typical VOL at VDD = 5V (standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

Figure 143. Typical VOL at VDD = 5V (high-sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

Figure 144. Typical VDD -VOH at VDD = 5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332

Figure 145. RESET pin protection when LVD is enabled(1)(2)(4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333

Figure 146. RESET pin protection when LVD is disabled(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334

Figure 147. Two typical applications with VPP pin(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334

Figure 148. SPI slave timing diagram with CPHA = 0(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337

Figure 149. SPI slave timing diagram with CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337

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