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ST7MC1K2-Auto 数据表(PDF) 66 Page - STMicroelectronics |
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ST7MC1K2-Auto 数据表(HTML) 66 Page - STMicroelectronics |
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66 / 371 page  Obsolete Product(s) - Obsolete Product(s) Interrupts ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto 66/371 Caution: If the I1_x and I0_x bits are modified while the interrupt x is executed the following behavior has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is higher than the previous one, the interrupt x is re-entered. Otherwise, the software priority stays unchanged up to the next interrupt request (after the IRET of the interrupt x). 7.6 Interrupt instructions 7.7 External interrupts The pending interrupts are cleared writing a different value in the ISx[1:0], IPA or IPB bits of the EICR. Note: External interrupts are masked when an I/O (configured as input interrupt) of the same interrupt vector is forced to VSS. 7.7.1 I/O port interrupt sensitivity The external interrupt sensitivity is controlled by the IPA, IPB and ISxx bits of the EICR register (Figure 20). This control allows to have up to four fully independent external interrupt source sensitivities. Each external interrupt source can be generated on four (or five) different events on the pin: ● Falling edge ● Rising edge ● Falling and rising edge ● Falling edge and low level ● Rising edge and high level (only for ei0 and ei2) To guarantee correct functionality, the sensitivity bits in the EICR register can be modified only when the I1 and I0 bits of the CC register are both set to 1 (level 3). Table 19. Dedicated interrupt instruction set(1) 1. During the execution of an interrupt routine, the HALT, popCC, RIM, SIM and WFI instructions change the current software priority up to the next IRET instruction or one of the previously mentioned instructions. Instruction New description Function/example I1 H I0 N Z C HALT Entering Halt mode 1 0 IRET Interrupt routine return Pop CC, A, X, PC I1 H I0 N Z C JRM Jump if I1:0 = 11 (level 3) I1:0 = 11 ? JRNM Jump if I1:0 <> 11 I1:0 <> 11 ? Pop CC Pop CC from the stack Mem => CC I1 H I0 N Z C RIM Enable interrupt (level 0 set) Load 10 in I1:0 of CC 1 0 SIM Disable interrupt (level 3 set) Load 11 in I1:0 of CC 1 1 TRAP Software TRAP Software NMI 1 1 WFI Wait for interrupt 1 0 Obsolete Product(s) - Obsolete Product(s) |
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