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ST7MC1K2-Auto 数据表(PDF) 64 Page - STMicroelectronics |
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ST7MC1K2-Auto 数据表(HTML) 64 Page - STMicroelectronics |
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64 / 371 page  Obsolete Product(s) - Obsolete Product(s) Interrupts ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto 64/371 7.5 Interrupt registers 7.5.1 CPU CC register interrupt bits CPU CC register Reset value: 111x 1010 (xAh) 7 654 32 10 1I1 H I0 N Z C R/W R/W R/W R/W R/W R/W R/W Table 17. CPU CC register interrupt bits description Bit Name Function 5, 3 I1, I0 Software interrupt priority These two bits indicate the current interrupt software priority: 10: Interrupt software priority = level 0 (main) 01: Interrupt software priority = level 1 00: Interrupt software priority = level 2 11: Interrupt software priority = level 3 (interrupt disable)(1) These 2 bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (ISPRx). They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and push/pop instructions (see Table 19: Dedicated interrupt instruction set). 1. MCES, TRAP and reset events can interrupt a level 3 program. Obsolete Product(s) - Obsolete Product(s) |
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