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ST7MC1K2-Auto 数据表(PDF) 77 Page - STMicroelectronics |
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ST7MC1K2-Auto 数据表(HTML) 77 Page - STMicroelectronics |
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77 / 371 page  Obsolete Product(s) - Obsolete Product(s) ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto Power saving modes 77/371 Figure 27. Halt mode flowchart 1. WDGHALT is an option bit. See option byte section for more details. 2. Peripherals clocked with an external clock source can still be active. 3. Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to Table 22: Interrupt mapping on page 70 for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped. HALT instruction Reset Interrupt(3) Y N N Y Fetch reset vector or service interrupt 256 or 4096 CPU clock Watchdog Enable Disable WDGHALT(1) 0 Watchdog reset 1 (MCCSR.OIE = 0) cycle delay CPU Oscillator Peripherals(2) I[1:0] bits Off Off 10 Off CPU Oscillator Peripherals I[1:0] bits On Off XX(4) On CPU Oscillator Peripherals I[1:0] bits On On XX(4) On Obsolete Product(s) - Obsolete Product(s) |
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