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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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ST7MC1K2-Auto 数据表(PDF) 46 Page - STMicroelectronics |
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ST7MC1K2-Auto 数据表(HTML) 46 Page - STMicroelectronics |
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46 / 371 page  Obsolete Product(s) - Obsolete Product(s) Supply, reset and clock management ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, 46/371 Figure 11. Reset block diagram 1. See Section 11.2.2: Illegal opcode reset on page 309 for more details on illegal opcode reset conditions. The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section. 6.4.3 External power-on reset If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until VDD is over the minimum level specified for the selected fOSC frequency. A proper reset signal for a slow rising VDD supply can generally be provided by an external RC network connected to the RESET pin. 6.4.4 Internal low voltage detector (LVD) reset Two different reset sequences caused by the internal LVD circuitry can be distinguished: ● Power-on reset ● Voltage drop reset The device RESET pin acts as an output that is pulled low when VDD <VIT+ (rising edge) or VDD <VIT- (falling edge) as shown in Figure 12. The LVD filters spikes on VDD larger than tg(VDD) to avoid parasitic resets. 6.4.5 Internal watchdog reset The RESET sequence generated by a internal watchdog counter overflow is shown in Figure 12. Starting from the Watchdog counter underflow, the device RESET pin acts as an output that is pulled low during at least tw(RSTL)out. Reset RON VDD Watchdog reset LVD reset Internal reset Pulse generator Filter Illegal opcode reset 1) Obsolete Product(s) - Obsolete Product(s) |
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