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ST7MC1K2-Auto 数据表(PDF) 74 Page - STMicroelectronics |
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ST7MC1K2-Auto 数据表(HTML) 74 Page - STMicroelectronics |
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74 / 371 page  Obsolete Product(s) - Obsolete Product(s) Power saving modes ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto 74/371 8.4 Active Halt and Halt modes Active Halt and Halt modes are the two lowest power consumption modes of the MCU. They are both entered by executing the ‘HALT’ instruction. The decision to enter either in Active Halt or Halt mode is given by the MCC/RTC interrupt enable flag (OIE bit in MCCSR register). 8.4.1 Active Halt mode Active Halt mode is the lowest power consumption mode of the MCU with a real time clock available. It is entered by executing the ‘HALT’ instruction when the OIE bit of the main clock controller status register (MCCSR) is set (see Section 6.6 on page 54 for more details on the MCCSR register). The MCU can exit Active Halt mode on reception of either an MCC/RTC interrupt, a specific interrupt (see Table 22: Interrupt mapping on page 70) or a reset. When exiting Active Halt mode by means of an interrupt, no 256 or 4096 CPU cycle delay occurs. The CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 25). When entering Active Halt mode, the I[1:0] bits in the CC register are forced to ‘10b’ to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately. In Active Halt mode, only the main oscillator and its associated counter (MCC/RTC) are running to keep a wake-up time base. All other peripherals are not clocked except those which get their clock supply from another clock generator (such as external or auxiliary oscillator). The safeguard against staying locked in Active Halt mode is provided by the oscillator interrupt. Note: As soon as the interrupt capability of one of the oscillators is selected (MCCSR.OIE bit set), entering Active Halt mode while the watchdog is active does not generate a reset. This means that the device cannot spend more than a defined delay in this power saving mode. Figure 24. Active Halt timing overview 1. This delay occurs only if the MCU exits Active Halt mode by means of a reset. Table 23. Active Halt and Halt power saving modes MCCSR OIE bit Power saving mode entered when HALT instruction is executed 0 Halt mode 1 Active Halt mode HALT Run Run 256 or 4096 CPU cycle delay (1) Reset or interrupt HALT instruction Fetch vector Active [MCCSR.OIE = 1] Obsolete Product(s) - Obsolete Product(s) |
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