ST7MC1K2-Auto datasheet(50/371 Pages) STMICROELECTRONICS

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Supply, reset and clock management

ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto,

50/371

Figure 14.

Using the AVD to monitor VDD

6.5.3

Clock security system (CSS)

The clock security system (CSS) protects the ST7 against main clock problems. To allow the

integration of the security features in the applications, it is based on a PLL which can

provide a backup clock. The PLL can be enabled or disabled by option byte or by software. It

requires an 8-MHz input clock and provides a 16-MHz output clock.

Safe oscillator control

The safe oscillator of the CSS block is made of a PLL.

If the clock signal disappears (due to a broken or disconnected resonator) the PLL continues

to provide a lower frequency, which allows the ST7 to perform some rescue operations.

Note:

The clock signal must be present at start-up. Otherwise, the ST7MC1K2-Auto,

ST7MC1K26Auto, ST7MC2S4-Auto, and ST7MC2S6-Auto do not start and are maintained

in reset conditions.

Limitation detection

The automatic safe oscillator selection is notified by hardware setting the CSSD bit of the

SICSR register. An interrupt can be generated if the CSSIE bit has been previously set.

These two bits are described in the SICSR register description.

VDD

VIT+(AVD)

VIT-(AVD)

AVDF bit

AVDIE bit = 1

Vhyst

AVD interrup

request if

Interrupt process

VIT+(LVD)

VIT-(LVD)

LVD RESET

Early warning interrupt

(power has dropped, MCU not yet in reset)

trv voltage rise time

Interrupt process

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Product(s)

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