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ST7MC1K2-Auto 数据表(PDF) 90 Page - STMicroelectronics |
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ST7MC1K2-Auto 数据表(HTML) 90 Page - STMicroelectronics |
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90 / 371 page  Obsolete Product(s) - Obsolete Product(s) On-chip peripherals ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto 90/371 Figure 33. Window watchdog timing diagram 10.1.6 Low power modes 10.1.7 Hardware watchdog option If Hardware watchdog is selected by option byte, the watchdog is always active and the WDGA bit in the WDGCR is not used. Refer to Section 14.1: Flash option bytes. T6 bit Reset WDGWR T[5:0] CNT downcounter time Refresh window Refresh not allowed (step = 16384/fOSC2) 3Fh Table 34. Effect of low power modes on window watchdog Mode Description Slow No effect on watchdog. The downcounter continues to decrement at normal speed. Wait No effect on watchdog. The downcounter continues to decrement. Halt OIE bit in MCCSR register WDGHALT bit in option byte 00 No watchdog reset is generated. The MCU enters Halt mode. The watchdog counter is decremented once and then stops counting and is no longer able to generate a watchdog reset until the MCU receives an external interrupt or a reset. If an interrupt is received (refer to Table 22: Interrupt mapping to see interrupts which can occur in Halt mode), the watchdog restarts counting after 256 or 4096 CPU clocks. If a reset is generated, the watchdog is disabled (reset state) unless hardware watchdog is selected by option byte. For application recommendations see Section 10.1.8 below. 0 1 A reset is generated instead of entering Halt mode. Active Halt 1 x No reset is generated. The MCU enters Active Halt mode. The watchdog counter is not decremented. It stops counting. When the MCU receives an oscillator interrupt or external interrupt, the watchdog restarts counting immediately. When the MCU receives a reset the watchdog restarts counting after 256 or 4096 CPU clocks. Obsolete Product(s) - Obsolete Product(s) |
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