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ST7MC1K2-Auto 数据表(PDF) 61 Page - STMicroelectronics |
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ST7MC1K2-Auto 数据表(HTML) 61 Page - STMicroelectronics |
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61 / 371 page  Obsolete Product(s) - Obsolete Product(s) ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto Interrupts 61/371 Figure 17. Priority decision process When an interrupt request is not serviced immediately, it is latched and then processed when its software priority combined with the hardware priority becomes the highest one. Note: 1 The hardware priority is exclusive while the software one is not. This allows the previous process to succeed with only one interrupt. 2 Reset, TRAP and MCES can be considered as having the highest software priority in the decision process. 7.2.2 Different interrupt vector sources Two interrupt source types are managed by the ST7 interrupt controller: the non-maskable type (reset, TRAP) and the maskable type (external or from internal peripherals). 7.2.3 Non-maskable sources These sources are processed regardless of the state of the I1 and I0 bits of the CC register (see Figure 16). After stacking the PC, X, A and CC registers (except for reset), the corresponding vector is loaded in the PC register and the I1 and I0 bits of the CC are set to disable interrupts (level 3). These sources allow the processor to exit Halt mode. ● TRAP (non maskable software interrupt) This software interrupt is serviced when the TRAP instruction is executed. It is serviced according to the flowchart in Figure 16 as a MCES top level interrupt. ● Reset The reset source has the highest priority in the ST7. This means that the first current routine has the highest software priority (level 3) and the highest hardware priority. See Section 6.4: Reset sequence manager (RSM) for more details. Pending Software Different interrupts Same Highest hardware priority serviced priority Highest software priority serviced Obsolete Product(s) - Obsolete Product(s) |
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