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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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ST7MC1K2-Auto 数据表(PDF) 30 Page - STMicroelectronics |
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ST7MC1K2-Auto 数据表(HTML) 30 Page - STMicroelectronics |
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30 / 371 page  Obsolete Product(s) - Obsolete Product(s) Register and memory map ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto 30/371 002Ch 002Dh MCC MCCSR MCCBCR Main clock control/status register Main clock controller/beep control register 00h 00h R/W R/W 002Eh 002Fh 0030h ADC ADCCSR ADCDRMSB ADCDRLSB Control/status register Data register MSB Data register LSB 00h 00h 00h R/W Read only Read only 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh Timer A TACR2 TACR1 TACSR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR Timer A control register 2 Timer A control register 1 Timer A control/status register Timer A input capture 1 high register Timer A input capture 1 low register Timer A output compare 1 high register Timer A output compare 1 low register Timer A counter high register Timer A counter low register Timer A alternate counter high register Timer A alternate counter low register Timer A input capture 2 high register Timer A input capture 2 low register Timer A output compare 2 high register Timer A output compare 2 low register 00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h R/W R/W R/W Read only Read only R/W R/W Read only Read only Read only Read only Read only Read only R/W R/W 0040h SIM SICSR System integrity control/status register 000x000x b R/W 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh TIMER B TBCR2 TBCR1 TBCSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR TBOC2LR Timer B control register 2 Timer B control register 1 Timer B control/status register Timer B input capture 1 high register Timer B input capture 1 low register Timer B output compare 1 high register Timer B output compare 1 low register Timer B counter high register Timer B counter low register Timer B alternate counter high register Timer B alternate counter low register Timer B input capture 2 high register Timer B input capture 2 low register Timer B output compare 2 high register Timer B output compare 2 low register 00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h R/W R/W R/W Read only Read only R/W R/W Read only Read only Read only Read only Read only Read only R/W R/W Table 3. Hardware register map (continued) Address Block Register label Register name Reset status Remarks Obsolete Product(s) - Obsolete Product(s) |
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