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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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ST7MC1K2-Auto 数据表(PDF) 72 Page - STMicroelectronics |
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ST7MC1K2-Auto 数据表(HTML) 72 Page - STMicroelectronics |
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72 / 371 page  Obsolete Product(s) - Obsolete Product(s) Power saving modes ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto 72/371 8.2 Slow mode This mode has two targets: ● To reduce power consumption by decreasing the internal clock in the device, ● To adapt the internal clock frequency (fCPU) to the available supply voltage. SLOW mode is controlled by three bits in the MCCSR register: the SMS bit enables or disables SLOW mode and two CPx bits select the internal slow frequency (fCPU). In this mode, the master clock frequency (fOSC2) can be divided by 2, 4, 8 or 16. The CPU and peripherals are clocked at this lower frequency (fCPU). Note: Slow Wait mode is activated when entering the Wait mode while the device is already in Slow mode. Figure 22. SLOW mode clock transitions 00 01 SMS CP1:0 fCPU New SLOW Normal run mode MCCSR frequency request request fOSC2 fOSC2/2 fOSC2/4 fOSC2 Obsolete Product(s) - Obsolete Product(s) |
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