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ST7MC1K2-Auto 数据表(PDF) 62 Page - STMicroelectronics |
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ST7MC1K2-Auto 数据表(HTML) 62 Page - STMicroelectronics |
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62 / 371 page  Obsolete Product(s) - Obsolete Product(s) Interrupts ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto 62/371 7.2.4 Maskable sources Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in ISPRx registers) is higher than the one currently being serviced (I1 and I0 in CC register). If any of these two conditions is false, the interrupt is latched and thus remains pending. ● MCES (MTC emergency stop): This hardware interrupt occurs when a specific edge is detected on the dedicated MCES pin or when an error is detected by the micro in the motor speed measurement. The interrupt request is maintained as long as the MCES pin is low if the interrupt is enabled by the EIM bit in the MIMR register. ● External interrupts: External interrupts allow the processor to exit from HALT low power mode. External interrupt sensitivity is software selectable through the external interrupt control register (EICR). External interrupt triggered on edge is latched and the interrupt request automatically cleared upon entering the interrupt service routine. If several input pins of a group connected to the same interrupt line are selected simultaneously, these are logically ORed. ● Peripheral interrupts: Usually the peripheral interrupts cause the MCU to exit from Halt mode except those mentioned in Table 22: Interrupt mapping. A peripheral interrupt occurs when a specific flag is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register. The general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. Note: The clearing sequence resets the internal latch. Therefore, a pending interrupt (that is, an interrupt waiting to be serviced) is lost if the clear sequence is executed. 7.3 Interrupts and low power modes All interrupts allow the processor to exit the Wait low power mode. On the contrary, only external and other specified interrupts allow the processor to exit from the Halt modes (see column ‘exit from HALT’ in Table 22: Interrupt mapping). When several pending interrupts are present while exiting Halt mode, the first one serviced can only be an interrupt with exit from Halt mode capability and it is selected through the same decision process shown in Figure 17. Note: If an interrupt, that is not able to exit from Halt mode, is pending with the highest priority when exiting Halt mode, this interrupt is serviced after the first one serviced. Obsolete Product(s) - Obsolete Product(s) |
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